\subsection{\index{dbitrev}dbitrev}

\index{double bit reverse}
Double BIT REVerse


\begin{tabular}{l}
  {\bf dbitrev r3, r2, r1} \\
  {\bf dbitrev r2, r1}\\
  {\bf sdbitrev r3, r2, r1} \\
  {\bf sdbitrev r2, r1}\\
\end{tabular}

~~~~~~
Computes r1 = bit\_reverse(r2) {\htmlGt}{\htmlGt} (\~r3 \% size),\\
r1\^1 = bit\_reverse(r2) {\htmlLt}{\htmlLt} (\~r3 \% size)

by default r3 == r0\\

~~~~~~
R2 is first bit-reversed then shifted right \~r3 \% size times.

~~~~~~
The value of r3 is truncated to the number of bits needed by the bit shuffler 
unit. Because it is aimed at pointer manipulation, the SIMD flag is not used.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_DBITREV
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20-18
} & {(none yet)
} & {0
} & {Reserved
}
\\ \hline

\end{tabular}


~

{\bf Example :}
\end{center}


R1 contains 0x08 (a 256-byte buffer)\\
R2 contains 0x48 (the current index)\\
R3 contains 0xFF05891213450100 (the buffer base address)

{\tt
{\bf bitrev r1,r2,r3 }: r3 = 0x0C\\
{\bf bitrevo r1,r2,r3 }: r4 = 0xFF0589121345010C\\
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Bit Shuffling Unit\\
{\em Latency :} 1 cycle\\
{\em Throughput :} 1 per cycle per BSU.\\

~

\pagebreak


