\subsection{\index{bitrev}bitrev}

\index{bit reverse}
BIT REVerse


\begin{tabular}{l}
  {\bf bitrev[o] (r3,) r2, r1} \\
  {\bf sbitrev[o] (r3,) r2, r1} \\
\end{tabular}

~~~~~~
Computes r1 = bit\_reverse(r2) {\htmlGt}{\htmlGt} (\~r3 \% size)\\
or r1\^1 = r1 {\htmlBar} ( bit\_reverse(r2) {\htmlGt}{\htmlGt} (\~r3 \% size)

by default r3 == r0\\

~~~~~~
R2 is first bit-reversed then shifted right size - r3 times.

~~~~~~
If the -o flag is set, the result is combined by a OR with the content of r1 
before it is written back to r1\^1. This instruction is used to compute pointer 
updates in butterfly data structures, where r3 is the log2 of the size of the 
structure, r2 is the current index in the structure (always inferior to 
2{\htmlHat}r3) and r1 is the base pointer. It is a {\bf 3r1w} instruction form
and therefore optional.

~~~~~~
The value of r3 is truncated to the number of bits needed by the bit shuffler 
unit. Because it is aimed at pointer manipulation, the SIMD flag is not used. 
When a base address is used in conjunction with the -o flag, take care to align 
the base address to a boundray at least equivalent to the size of the data 
structure (just in case you weren't aware). In case the butterfly buffer is 
not aligned, an addition must be performed and the {\bf bitrev} instruction 
must be used instead. The alignment of the final data is ensured by limiting 
the index : for example, a 256-byte buffer with 32-bit words requires that the 
index is between 0 and 63, so the final 2 LSB are always cleared.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_BITREV
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {-o postfix
} & {1 if set
} & {OR the result with the destination
 } \\
 \hline
\multicolumn{1}{|c| }{19-18
} & {(none yet)
} & {0
} & {Reserved
}
\\ \hline

\end{tabular}


~

{\bf Example :}
\end{center}


R1 contains 0x08 (a 256-byte buffer)\\
R2 contains 0x48 (the current index)\\
R3 contains 0xFF05891213450100 (the buffer base address)

{\tt
{\bf bitrev r1,r2,r3 }: r3 = 0x0C\\
{\bf bitrevo r1,r2,r3 }: r4 = 0xFF0589121345010C\\
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Bit Shuffling Unit\\
{\em Latency :} 1 cycle\\
{\em Throughput :} 1 per cycle per BSU.\\

~

\pagebreak


