\chapter{Frequently Asked Questions}
 
 Collected from different sources. Last modified by Whygee, jan, 14 2000

\section{Introduction}
\begin{list}{}{}
 \item \underline{Q1 : What is the F-CPU ?}
 \item   A : The F-CPU is a inherently SIMD, 64-bit, superpipelined microprocessor,
    available with VHDL source code and distributed under the terms of the
    GNU Public Licence. It is being developped by a community of hobbyists,
    students and professionals on the Internet.

~

\ULforem
\item \emph{Q2 : Why a 64-bit RISC CPU ? I want to make a x86 clone~/ a soundcard~/
a 32-bit embedded core ...}

 \item A : \url{http://www.opencollector.org}

 \item The original goal of a high performance 64-bit CPU dates back to the early
days of the project when the founders wanted to counter the Merced (ia64). If you desire
something else, there is a great chance that a project already exists with a goal
similar to your requirements. The OpenCollector is one of the websites that list the
``free'' projects that you can access on the Internet. If you don't find what you want,
don't hesitate to create your own project.

 There are already a lot of free CPU projects available on the Internet.
If you desire a 32-bit-only CPU, the MIPS/DLX and the \index{LEON}LEON CPUs are good starting points,
even though the F-CPU can be easily scaled down to 32 bits. If you require a 16-bit or
8-bit microcontroller, there are also a lot of free (in different ways) designs. You
just have to pick one from the lists of the OpenCollector website. If you are sure that
you want a F-CPU-like processor, be sure to read and understand this manual before you
go further in your project. The goals of the project are firm and will not change because
of an individual's whim.

~

\end{list}

\section{Philosophy}
\begin{list}{}{}
 \item \underline{Q1 : What does the F in F-CPU stand for ?}
 \item A : It stands for \index{Freedom}Freedom, which is the original name of the architecture,
               or Free, in the GNU/GPL sense.

 \item  The F does not stand for free in a monetary sense. "Free" doesn't mean "free as
        free beer" but "freely copiable and modifiable". You will have to pay for the chip, 
        just as you have to pay nowadays for a copy of a GNU/Linux distribution on CD-ROMs. 
    	Of course, you're free to take the design and masks to your favorite fab and have a few 
	batches manufactured for your own use.
\newpage

 \item \underline{Q2 : Why not call it an O-CPU (where O stands for Open) ?}

  \item A : There are some fundamental philosophical differences between
            the \index{Open Source}Open Source movement and the original
	    \index{Free Software}Free Software movement. We abide
            by the latter, hence the F.

            The fact that a piece of code is labeled Open Source doesn't
            mean that your freedom to use it, understand it and improve upon it is
            guaranteed. Further discussion of these matters can be found at
            \url{htpp://www.gnu.org}.

            We tried to make a licence similar to the GPL (GNU Public Licence from the Free
            Software Foundation) (see \url{http://www.opencollector.org/hardlicense/})
            but this effort has been abandonned because it doesn't seem necessary or useful.
            Today it is replaced by an external charter that strengthens the meaning of the GPL.

            Specifically, there are at least three levels of freedom that
            must be preserved at any cost~:
			\begin{list}{-}{}
            \item  Freedom to use the Intellectual Property : no restriction must
                   exist to use the work of the F-CPU project. This means, no fee to access the
                   data and ALL the necessary informations to recreate a chip.
            \item  Freedom to reverse-engineer, understand and modify the Intellectual Property
                   at will.
            \item  Freedom to redistribute the design files.
			\end{list}

            This design is NOT public domain. The F-CPU group owns the IP that it produces.
            It chooses to make it freely available to anybody by any means.
            Every file or hardware generated from the description files and the Intellectual
            Property of the F-CPU team keeps the copyright of the F-CPU team. You can read
            more about it at \url{htpp://www.gnu.org}.

~

 \item \underline{Q3 : How is the F-CPU design protected ?}
 \item   A : The F-CPU Design Team protects his work with the copyright laws. Every file holds
        the copyright notice and the GPL notice. Nothing else is required.

 \item  Additional measures should ensure that no patent issue will arise in the future.
        Patents are well known for their inefficiency and high cost. The F-CPU design team
        is protected because it only describes the device, while issues appear when the design
        is implemented. We must publish proofs of prior art, during conferences and in the press,
        to avoid the remaining troubles. In the end, the design must remain totally unencumbered.

~

 \item \underline{Q4 : And what if I patent a feature of the F-CPU ?}
 \item   A : You will loose time and money, that's all.

 \item  First, the design is based on common techniques that are heavily studied for thirty
         years. You'll have a hard time explaining what is new enough to justify a patent.
 \item  Second, if the patent is accepted, noone will accept to pay the royalties on something
         that was stolen from the F-CPU team. Suing the implementors will lead to nothing and
         in the end, you will own a useless patent that gives you only worries.

~

\item \underline{Q5 : Why would my company use the F-CPU instead of another core ?}

\item A  : The technical advantages of the F-CPU are described in this manual :
 extreme scalability and orthogonality, ununcumbered and clean design, emphasis
 on performance, simplicity and retargetability to various technologies (FPGA/ASIC...)

 However the non-technical side of the project might ring a bell if you want to integrate
 the F-CPU core in your design. The design files are available at no charge, but it's
 not the only meaning of the ``free'' in the F-CPU. It is a transparent design, it is
 not a ``black box'' obfuscated by a proprietary and closed team. If you're in troubles,
 (for example : the design is deprecated, abandonned by the company or it runs out of
 business, in short : you're left alone with the design) you don't have to reverse-engineer
 the ``black box'' to figure out what goes wrong. You simply read the source code
 and patch it. The F-CPU is distributed under the terms of the GPL which gives you all
 the rights to understand and modify (customize) the files.

 Another aspect concerns the legal expenses. Just as the GPL is called a ``gentleman
 agreement'', the F-CPU is a ``gentleman's~CPU''. We promote peaceful collaboration
 between the teams~: more budget can be dedicated to research and design, less money
 is spent for the legal departments. In the end, everybody wins because the teams
 can be larger and spend all their time on the quality of the design and the time to
 market, rather than on expensive endless lawsuits. ``Design and let design'' : the
 only interesting and determining things are the reactiion time and the efficiency
 (cost, performance, ease of use) of the product.

~

\item \underline{Q6: Great but what are the fine lines ? Are there drawbacks ?}

\item A  : They are contained in the GPL and the F-CPU charter. Just as the design
 was brought to you free, you have to keep it free and redistribute all the modifications
 or additions to the core. Because the F-CPU (like all GPL projects) is based on
 collaboration/cooperation and not competition, your enhancements will benefit others
 but they can also enhance on your enhancements and this will benefit you in return.

 If you want to keep your design secret, don't integrate the F-CPU in your project.
 You will not be able to benefit from other's work and experience. You will have to
 reinvent the wheel and loose time and money.

~

\end{list}

\section{Tools}

\begin{list} {}{}

\item \underline{Q1 : Which EDA tools will you use ?}

\item  A : There has been a lot of debate on this subject. It's mainly a war between 
Verilog and VHDL. We have started with VHDL'93 for convencience because it is
most used in Europe (where most of the code is written) but it will certainly
be translated to other file formats. Currently, the design exists in VHDL'93 only
for convenience and uniformity. The other representations will be derived from it.
           
Now that VHDL is the main langage, VHDL tool choices are more limited.
We want to promote GNU EDA SW but this branch is not yet
developped or mature enough. A particular
software may be difficult to install, another may be unstable, outdated
or not compliant with today's standards and requirements.

The use of Alliance (\url{http://www-asim.lip6.fr/alliance/}) is considered
but it will be useful only during the layout process. Other free tools
and designs can be found from \url{http://www.opencollector.org}.

Today we use Simili (\url{http://www.symphonyeda.com}) under the Win32 platform.
It is not a GNU software but has many advantages such as independence,
compliance with the IEEE standard, ease of use, compacity... We expect
a Unix port in the future, as well as other good GNU EDA software.

The sources have also been compiled without modification with FreeHDL
and Modelsim. Other IEEE compliant compilers will certainly confirm the
high portability and quality of the design.

Cadence has just proposed free licences for some of its tools. Other offers will
probably follow and are welcome, as long as the "counterparts" are compatible
with the F-CPU charter.

We'll probably use commercial products at one point or another
because the chip makers use proprietary software. In any case,
a pen, paper and a brain always help.

~

\end{list}

\section{Architecture}

\begin{list}{}{}
\ULforem
\item \emph{Q1 : What's that memory-to-memory architecture I heard about ? Or this TTA engine ?
            Why not a register-to-register architecture like all other RISC processors ?}
			
\index{M2M}
\item  A : \textit{M2M} was an idea that was discussed at the beginning of the F-CPU project.
           It had several believed advantages over register-to-register architectures, like
            very low context switching latency (no registers to save and restore). Today,
            the SRB mechanism included in the FC0 solves this problem (see the Part IV,
            chapter 3, "The Smooth Register Backup mechanism").

\item  \textit{TTA} is another architecture that was explored before the current design
            (FC0) started.
\index{TTA}
\item  The F-CPU architecture might evolve in the future and borrow some new features
        of other architectures.


~

\item \underline{Q2 : You're thinking about an external FPU ?}
\index{FPU}
\item  A : No. Bandwidth and pin count problems. We can easily fit such units on a chip today.


~

\item \underline{Q3 : Why don't you support SMP ?}
\index{SMP}
\item A  : Symmetric Multi-Processing like it is implemented on low-end PCs limits
          the performance and scalability of the architecture. We're actively
          investigating other architectures, mainly Non-Uniform Memory Access
          through a specific bus called F-BUS. We try to avoid
          all the complex techniques needed by multi-CPU processing. No firm 
          decision has been made as of today. The F-CPU core is independent
          from the bus interface anyway, almost any type of connexion can be implemented.

~

\end{list}

\section{Performance}

\begin{list}{}{}

\item \underline{Q1 : What can we expect in terms of performance from the F1 CPU ?}
\index{Merced}
\item  A  : Merced-killer. :-). No seriously, we hope to get some serious performance, though it
   would be impossible to make any claim before we can measure the performance of a real chip.

\item   We think we can achieve good performance because we start from scratch (x86 is slower
        because it has to be compatible with older models).

\item  LINUX and GCC are not the best garanties for performance in themselves. For example, GCC
       doesn't handle SIMD data. We will certainly create a compiler that is more adapted to the
       F-CPU and GCC will be used as a "bootstrap" for the ``legacy SW'' at the beginning. The
       ongoing work on GNL and XML-based interfaces will probably allow developpers to create
       better code than what GCC would ever do.

\item Objectively, the FC0 core family is aimed to achieve the best MOPS/MIPS ratio possible,
around 1 (and maybe a bit more). The superpipeline garanties that the best clock
frequency is reached for any silicon technology. The memory bandwidth can be virtually
increased with different hint strategies. So we can predict that a 100MHz chip with 1
instruction decoded at each cycle can easily achieve 100 million operations per second.
Which is not bad at all because you can achieve that with an "older" (cheap) silicon
technology that couldn't achieve 100MOPS with a x86 architecture. Add to that the
unconstrained SIMD data width, and you get a picture of the peak MOPS it can reach.
If you really want screaming numbers, with a 64-bit version, SIMD operations on
bytes leads to 8 operations per cycle, or 800MOPS peak.

~

\end{list}

\section{Compatibility}

\begin{list}{}{}

\item \underline{Q1 : Will the F-CPU be compatible with x86 ?}
\index{x86}
\item  A : No. Nada. Niet. Nein. Non.

\item  There will be NO binary compatibility between the F-CPU and x86 processors.
       It could however run Windows emulators that include x86 CPU emulators such 
       as Twin, as well as Windows itself under whole-PC emulators such as Bochs. 
       In either case however you will need to run another operating system, such 
       as GNU/Linux, and emulation will likely be fairly slow. But what would be
       the point of using Windblows when you can run GNU-Linux/xBSD instead ? ;-D


~

\ULforem
\item \emph{Q2 : Will I be able to plug the F-CPU in a standard Socket 7, Super 7, Slot 1,
         Slot 2, Slot A or any other existing motherboard ?}

\item  A : Great chances are that no version of the F-CPU will ever be available for Socket7
            or any x86 mother boards.
       \begin{list}{}{}
       \item  Reason 1 : the BIOS should be rewritten, the chipsets should be analysed,
                  and there are way too many chipsets/motherboards combinations around.
                  It is clearly out of the scope of our project.
       \item  Reason 2 : Socket/pins/bandwidth : the x86 chips are really "memory bound",
                 the bandwidth is too low, some pins are not useful for a non-x86 chip,
                 and supporting all the functions of the x86 interface will make
                 the chip (its design and debugging) too complex, more expensive and slower.
       \item  Reason 3 : we don't want to pay the fees for the use of proprietary slots.
       \end{list}
\index{ALPHA}\index{MIPS}\index{EV-4}
\item  ALPHA- or MIPS-like slots will probably be supported, we might include an EV-4 interface
       to the F-CPU standard.  Anyway, a custom socket and interface will avoid any
       compatibility and misunderstanding problem. If you want to plug your F-CPU chip on
       something else, ``just do it''.


~


\item \underline{Q3 : What OS kernels will the F-CPU support?}
\index{OS}\index{Linux}
\item  A : Linux will probably be ported first. Other ports will follow and different 
       kernel types are possible. But first we must have a working software development
       tool for the architecture, thus we must first fully define the F-CPU ...


~


\item \underline{Q4 : What programs will I be able to run on the F-CPU ?}

\item  A : We have a first prototype/preliminary port of gcc/egcs for the Freedom architecture.
           Basically the F-CPU will run all the software available for a standard GNU/Linux
           distribution, except the low-level parts such as assembly, I/O and bootstrap code.

\item  Remember that GCC is not perfectly adapted to fifth generation CPUs. We have adapted it
        for the F-CPU but it was very difficult and it supports only a small subset of the
        capabilities of the F-CPU ISA. Don't expect good performance from the generated
        code, at least for the FC0.

~

\end{list}


\section{Cost/Price/Purchasing}
\index{Cost}\index{Price}\index{Purchasing}
\begin{list}{}{}

\item \underline{Q1 : Will I be able to buy a F-CPU someday ?}

\item A : We hope so. That's all the point of the project, but be patient and take part
of the discussions~! If you think it is not developped fast enough, join the team and
help us. Before the F-CPU will exist in a chip, it will be available in other forms such
as software or hardware emulations or simulations.


~


\item \underline{Q2 : How much will the F-CPU cost ?}

\item  A : We don't know. It depends on how many are made. There was an early slightly
    optimistic estimate that an F-CPU would cost approximately \$100, if 10000 were made.
    This also depends on a lot of factors like the desired performance, the size of the
    cache memory, the number of pins, and most of all, the possibility to combine all these
    factors in the available technology. The latest estimations for a first limited version
    gave around \$60 each for a batch of 1K ASIC. The FC0 chip looks a bigger and simplified
    486, it belongs to the class of 1 million transistors chips. It is more than the LEON
    core or the ARM, but it is small compared to other 64 bit chips. Therefore it shouldn't
    be as expensive as a high-end CPU.
\index{LEON}\index{ARM}

~

\end{list}
