\chapter{\index{evolution}Evolution of the FC0}

 Discussion after discussion, the \index{FC0}FC0 has taken a shape that makes it unique. Because it is a
gradual change, and because there is not only one view of the processor structure, there have
been several drawings that show the internal organization of the chip.

\begin{figure}[H]
  \begin{center}
    \includegraphics[width=12cm,draft=false]{F1.eps}
     \caption{The first \index{F-CPU}F-CPU chip proposal}
  \end{center}
\end{figure}

The figure 2.1 is the first drawing that shows the general shapes of the FC0,
from the schematic,
functional and implementation points of view. At that time, the Xbar did not count for a full
clock cycle in the pipeline. The memory hierarchy was not designed and consisted of empty
"units". The execution pipeline though was almost determined and did not change much.

\begin{figure}[H]
  \begin{center}
    \includegraphics[width=17cm,draft=false]{F1-2.eps}
    \caption{A more precise, first-attempt F-CPU description}
  \end{center}
\end{figure}

 The figure 2.2 shows how the units that access the memory would be architected. These are still
at both extremities of the chip and require very long wires to snoop for data/instruction access
conflicts. The memory units are explicited though, and consist of several cache line buffers.
A curious feature is that the address "fences" (that store the base address and limit size of
the blocks that a task is allowed to access) are inside the memory units, the TLBs are now
outside of the units. The Xbar now takes a full clock cycle and is considered as a full unit,
the execution pipeline is refined. Due to the ongoing discussions, the register set had only
two read and two write ports, the third read port was accepted later.

\begin{figure}[H]
  \begin{center}
    \includegraphics[width=16cm,draft=false]{F1-3.eps}
    \caption{A third F-CPU description}
  \end{center}
\end{figure}

 The figure 2.3 shows the current status of the \index{FC0}FC0 as it is envisionned for the 
\index{F1}F1. The memory units have been gathered so the wires that drive the address and data 
lines outside of the chip have a minimal length. They are symmetrically positionned so the tags 
of the cache line buffers can all be compared in one simple unit that decides and schedules the 
memory accesses. The data and instruction TLBs are separated from the memory units because they 
are parts of the pipeline, and should be placed close to the decoding unit in order to signal 
an invalid pointer as soon as possible.

\begin{figure}[H]
  \begin{center}
    \includegraphics[width=16cm,draft=false]{FC0layout.eps}
    \caption{The current F-CPU diagram}
  \end{center}
\end{figure}

 The figure 2.4 is the latest update : the external data bus has been split into 2
x 64-bit \index{SDRAM}SDRAM buses, the \index{POPCOUNT}POPCOUNT unit is added and the memory
system (\index{TLB}TLB/\index{LUT}LUT/\index{cache}cache etc.) is even more precise. We can 
see that the overall shape doesn't change much but is refined.
