Lab 6

Design of FIR filter

Introduction:

FIR (Finite Impulse Response) filter is one of the most widespread numerical filters. They are used practically everywhere in numerical signal processing including mobile phones. The name of the filter comes from the fact, that single pulse passes the filter within finite amount of time. This time depends on the filter order, what is the number of used coefficients. The testing of this filter is based on the following feature – give to the input single pulse and in some amount of time in the output you must see all filter coefficients values. The same way is tested filter example “lab6firBeh.vhd” (wave diagram is given below). You would design FIR filter with order of nine, this means design function is data_out= å c_i * data_in^i-1, where i=1, 2, …, 9 and data_in^-i is delay for i cycles of input data_in.

In this lab everybody gets their own task, however a lot of basic solutions coincide. Therefore teamwork is welcome. The difference of tasks is in values of coefficients, which you can find according to your matriculation number – rest of division with 2, 3, 4, 5 and 7 gives you one of the coefficients according to the table below. The filter is symmetrical (c₁=c₉), thus order of indexes (incremental or decremental) is not important.

Divisor ->	3	4	7	5	2
Rest	c1, c9	c2, c8	c3, c7	c4, c6	c5
0	0.125	0.25	-0.75	1.25	1.0
1	-0.125	-0.25	0.75	-1.25	1.25
2	0.25	0.5	-0.625	0.75
3		-0.5	0.625	-0.75
4			0.875	0.875
5			-0.875
6			1.125

Initial data:

· 16 – bit fixed point data: sign bit, 5 bits at the left side of point, 10 bits at the right side of point;

· Filter’s order is 9, coefficients could be found from the table above;

· Entity is defined as the following:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity fir_filter is
 port ( data_in: in signed (15 downto 0);
 data_out: out signed (15 downto 0);
 sample, clk: in bit );

end fir_filter;

· All calculations must be performed in 4 cycles (signal clk)

· Input and output of the data occur only if signal sample is true (not faster than every fourth cycle)

Tasks:

· Create behavioral module with your coefficients and testbench for it. You can take code in file lab6firBeh.vhd as basis for your module. Simulate and make sure that module works correctly (compare with the diagram below)

· Choose architecture (use the easiest computational units as possible), transform operations (if it is needed), schedule operations among cycles, create necessary registers, bind operations to resources (your computational units). According results of scheduling and binding write corresponding RTL code. The example of the RTL code can be taken from lab6firRtl.vhd. Simulate RTL code to check the correctness of behavior.

· Synthesize your FIR filter with clock period 20 ns. If it is necessary change the code in order to get the smallest possible area.

Report:

Your report should contain:

· Behavioral and RTL VHDL code, testbench code;

· Simulation results (behavioral and RTL);

· Made transformations: transformations of operations, scheduling and binding of operations;

· Synthesis results (area, delay, number of registers) and analysis, especially in case delay 20 ns is not achieved.

Hints:

· To output real number: “debug_out<=real(conv_integer(data_out))/1024.0;”

· 5 * a == 4*a + a == (a<<2) + a;

· In division the round-up is not important;

· To test the behavior the pulse with value 1.0 (0400₁₆) suits the best (see wave diagram below);

· 16-bit adder’s approximate parameters: small-slow – area 124, delay 19 ns; quick- big – area 570, delay 5.9 ns;

· 16-bit multiplexer approximate parameters: small-slow – area 2080, delay 36 ns; quick-big – area 3860, delay 21 ns.

Wave diagram with input of pulse with value 1.0

One possible solution example