-- Address generator

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity agener is
  generic ( bitwidth: positive );
  port (
    clock: in bit;
    reset, enable: in std_logic;
    start_address, stop_address: in unsigned(bitwidth-1 downto 0);
    address: out unsigned(bitwidth-1 downto 0) );
end agener;


architecture one_direction of agener is
signal counter: unsigned(bitwidth -1 downto 0);
begin

process 
begin
	wait on clock until clock='1';
	if(reset='1') then 
		counter<=start_address;
	elsif(enable='1') and (counter<stop_address)then 
		counter<=counter+1;
	end if;
	address<=counter;
end process;

	

end one_direction;