Lab 4

Intelligent testbench for elevator controller

 

 

During this lab you are going to write intelligent testbench for elevator controller, which was designed in the previous lab.

To perform this task you need the design of elevator controller (supposed it is ready from the previous lab) and you get empty testbench at_elevator.vhd, which you need to finish.

In order to complete this intelligent testbench it is required to add the procedure, which task is to call the elevator from the usual user’s point of view and to test whether the behavior of the elevator controller is correct.

User’s point of view:

1.     person is on some floor in the building and wants to call the elevator, therefore person presses a button on the floor;

2.     person waits for the elevator, when it is on user’s floor person enters

3.     and presses the button inside the lift car indicating where he/she wishes to go.

 

Therefore procedure has 2 main parameters of type integer: floor number where person is and floor number where person wants to go. Besides it has as parameters all needed signals to interact with the elevator controller and one more parameter is delay of type time. The signature of this procedure is the following:

 

procedure CALL_ELEVATOR(USER_OUT_FLOOR, USER_IN_FLOOR: in integer;

constant DELAY: in TIME;

signal MOT: in bit_vector(0 to 1);

signal DOORS: in bit_vector(1 to NUM_FLOORS);

signal FLOOR_NUM: in integer;

signal BUT_IN, BUT_OUT: out bit_vector(1 to NUM_FLOORS));

 

In order to test the behavior of the elevator controller inside the procedure, you need to control:

1.     whether elevator goes up or down when the corresponding button is pressed and report a warning if not;

2.     whether elevator stops on called floor, opens doors and report an error if not;

3.     whether elevator goes up or down when the corresponding button inside the lift car is pressed and report a warning if not;

4.     whether elevator stops on called floor, opens doors and report an error if not;

5.     (you can add some other control situations if you wish).

 

In order to check the direction of the elevator we need to know the floor where the elevator is at the moment, therefore you need to add to your design of elevator controller one more output port FLOOR_NUM of type integer, its function is to show the current floor of the elevator (don’t forget to bind this port with proper signal inside the design).

 

You can use the following construction of VHDL language to report the messages:

 

assert([condition]) report [string message] severity [NOTE, WARNING, ERROR, FAILURE];

To report values of signals or variable you can use:

[scalar type]’image([signal or variable name])

 

When the procedure is ready you can use it to control the behavior of the elevator controller. Run several concurrent processes, which call written procedure. The parameter DELAY indicates that user would press the button in DELAY amount of time. This parameter is added for the purpose of more complete testing.

When you try to write into signal concurrently you get unresolved behavior, because multiple sources are driving the same signal. As since we use the procedure concurrently the resolved function for signals BUTTONS_IN and BUTTONS_OUT is required. This function is ready for you and is added to empty testbench at_elevator.vhd.

The concurrent usage of the same signals BUTTONS_IN and BUTTONS_OUT with the help of CALL_ELEVATOR procedure instances could be graphically depicted as following:


 

 


Task:

 

Complete the testbench at_elevator.vhd:

·       Write the procedure CALL_ELEVATOR according to the description given above;

·       Check different situations by instantiating CALL_ELEVATOR as a concurrent procedure – several people use the elevator at the same time;

 

Requirements:

 

·       Code with comments added to the report;

·       Waveform picture added to the report;

·       Description of the situations for testing;

 

Questions:

 

·       Explain behavior of the resolved function WiredOR;

·       If we would use instead bit_vector type std_logic_vector type, what main changes would be inside this intelligent testbench?