Lab 1.

The purpose of this lab is to become acquainted with the Simulation tools of Mentor Graphics and Synopsys and make your choice, which to use forward. To get familiar with the tools vhdl files mux.vhd and t_mux.vhd are offered to you. Mux.vhd file is design file of multiplexer, which behavior is the following, if control signal JUHT_SIG is 1 then the input A_IN is propagated to the output OUT_SIG, if JUHT_SIG is 0 then input B_IN is propagated to the output. The schematic of multiplexer is in the Figure 1. t_mux.vhd is a testbench for the multiplexer design.

Figure 1 multiplexer diagram

Actions:

• Take the guide for Mentor Graphics simulator and try to compile first design file mux.vhd then testbench file t_mux.vhd, simulate the design and check the behavior. Design mux.vhd contains errors, fix the errors and make sure that behavior of the design is correct, if not try to fix the problem.
• Take the guide for Synopsys simulator and repeat the actions as for Mentor Graphics simulator
• Answer the questions

Questions:

• Explain the errors.
• Is it possible to get right waveforms of the signals during the simulation, even when your design contains behavioral errors? Give an example using lab files.