library IEEE;
use IEEE.std_logic_1164.all;

entity TB_MUX is
end TB_MUX;

architecture BENCH of TB_MUX is

  -- component declaration for MUX
  component MUX is
  port (A_IN     : in std_logic_vector(7 downto 0);
        B_IN     : in std_logic_vector(7 downto 0);
        JUHT_SIG : in  std_logic;
        OUT_SIG  : out std_logic_vector(7 downto 0));
  end component;

  -- local signal declarations
  signal A_IN_T, B_IN_T, OUT_SIG_T : std_logic_vector(7 downto 0);
  signal JUHT_SIG_T : std_logic;  

begin

  -- component instantiation of MUX
 MUX_COMP: MUX port map (A_IN_T, B_IN_T, JUHT_SIG_T, OUT_SIG_T);
 
  -- stimulus process
   STIMULUS: process
   begin
      A_IN_T     <= "00000000"; 
      B_IN_T     <= "11111111";
      JUHT_SIG_T <= '0';
      wait for 10 ns;

      JUHT_SIG_T <= '1';
      wait for 10 ns;

      A_IN_T  <= "00001111"; 
      B_IN_T  <= "11110000";
      JUHT_SIG_T  <= '0';
      wait for 10 ns;

      wait;  -- suspend process
   end process STIMULUS;

end BENCH;