------------------------------------------------------------------------------
--  File: t_counter.vhd
------------------------------------------------------------------------------

-- The test environment
entity test is
end test;

-- Content of the environment
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture  bench  of  test  is

  constant bw: integer := 4;
  signal clk: bit := '0';
  signal rst, ena: std_logic := '0';
  signal strt, stp, addr: unsigned(bw-1 downto 0) := (others=>'0');
  signal halt: boolean := false;

  -- Unit Under Test
  component agener
    generic ( bitwidth: positive );
    port (
      clock: in bit;
      reset, enable: in std_logic;
      start_address, stop_address: in unsigned(bitwidth-1 downto 0);
      address: out unsigned(bitwidth-1 downto 0) );
  end component;

begin  --  bench

  -- UUT
  UUT: agener generic map (bw) port map (clk, rst, ena, strt, stp, addr);

  -- Clock generator
  clk <= not clk after 10 ns when not halt else unaffected;

  -- Test sequence
  process

    procedure MakeSequence
      ( constant start_value, stop_value, cycles_count: positive ) is
    begin
      wait on clk until clk='1';
      strt <= conv_unsigned ( start_value, bw ) after 1 ns;
      stp  <= conv_unsigned ( stop_value, bw ) after 1 ns;
      rst <= '1' after 1 ns;    ena <= '0' after 1 ns;
      wait on clk until clk='1';
      rst <= '0' after 1 ns;
      wait on clk until clk='1';
      ena <= '1' after 1 ns;
      for i in 0 to cycles_count-4 loop
        wait on clk until clk='1';
      end loop;
      ena <= '0' after 1 ns;
      wait on clk until clk='1';
    end MakeSequence;

  begin
    MakeSequence ( 2, 12, 16 );  -- from 2 to 12, 16 cycles
    MakeSequence ( 13, 5, 16 );  -- from 13 down to 5, 16 cycles
    strt <= (others=>'0') after 1 ns;
    stp  <= (others=>'0') after 1 ns;
    halt <= true after 50 ns;
    wait;
  end process;

end bench;