Lectures

NB! The distribution of material between lectures may change, i.e., the boundaries are not fixed.

Lectures are given at every Thursday in IT-226 from 15:00 to 17:15.

No. Date  Topic
 .pdf 
1
31.01.
  Introduction. Myths.
2
2.02.
  Introduction to VHDL. Description styles, basic constructions.
3
9.02.
  Language constructions. Design stucturing.
4
16.02.
  Modelling of discrete systems.
5
2.03.
  Synthesizable VHDL.
6, 7
9.03. & 16.03.
  Verilog HDL.
8
23.03.
  Design methodology. Physical, logic, and register transfer level syntheses.
9
30.03.
  High-level synthesis. Scheduling (I).
10
6.04.
  Scheduling (II). Allocation and binding.
11
13.04.
  Local timing transformations - pipelining, retiming. System level synthesis.
12
20.04.
  System-on-Chip design.
13
27.04.
  The other hardware description languages.
14
4.05.
  Introduction to SystemC & VHDL-AMS.
-
11.05.
  Backup time-slot.
 

'*)' - lecture notes from previous year(s).
- Portable Document Format. to read/print files.

Last modified 2006.05.02