--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity DIST_TB is
end DIST_TB;

--**************************************************************************--

architecture BHV_DIST_TB of DIST_TB is

	component DIST
		port(rst : in STD_LOGIC;
		     clk : in STD_LOGIC;
		     start : in STD_LOGIC;
		     x : in UNSIGNED (7 downto 0);
		     y : in UNSIGNED (7 downto 0);
		     d : out UNSIGNED (3 downto 0);
		     done : out STD_LOGIC);
	end component;

	signal rst : STD_LOGIC := '0';
	signal clk : STD_LOGIC := '0';
	signal start : STD_LOGIC := '0';
	signal x : UNSIGNED (7 downto 0);
	signal y : UNSIGNED (7 downto 0);
	signal d : UNSIGNED (3 downto 0);
	signal done : STD_LOGIC;
begin

	U1 : DIST port map(rst, clk, start, x, y, d, done);

	x <= "01010101";
	y <= "01001010";

	process
	begin
		rst <= '1';
		wait for 10 ns;
		rst <= '0';
		wait for 10 ns;
		start <= '1';
		wait;
	end process;

	process
	begin
		clk <= not clk;
		wait for 10 ns;
	end process;
end BHV_DIST_TB;

--**************************************************************************--

configuration CFG_DIST_TB of DIST_TB is
	for BHV_DIST_TB
		for U1 : DIST use configuration WORK.CFG_DIST;
		end for;
	end for;
end CFG_DIST_TB;


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