--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity XS40 is 
	port(rst : in STD_LOGIC;
             clk : in STD_LOGIC;
             led : out STD_LOGIC_VECTOR (6 downto 0));
end XS40;

--**************************************************************************--

architecture XS40_ARCH of XS40 is

	component WRLED
		port(val : in UNSIGNED (3 downto 0);
		     led : out STD_LOGIC_VECTOR (6 downto 0));
	end component;

	constant C0_4 : UNSIGNED (3 downto 0) := "0000";
	constant C1_4 : UNSIGNED (3 downto 0) := "0001";
	constant CM_4 : UNSIGNED (3 downto 0) := "1111";
	
	constant C0_24 : UNSIGNED (23 downto 0) := "000000000000000000000000";
	constant C1_24 : UNSIGNED (23 downto 0) := "000000000000000000000001";
	constant CM_24 : UNSIGNED (23 downto 0) := "101101110001101100000000";
		
	signal val : UNSIGNED (3 downto 0);
	signal i : UNSIGNED (23 downto 0);
begin
	U1 : WRLED port map(VAL, LED);
	
	process(rst, clk)
	begin
		if( rst = '0' ) then

			val <= C0_4;
			i <= C0_24;
		elsif( clk'event and clk = '1' ) then

			if( i = CM_24 ) then
			
				i <= C0_24;
				if( val = CM_4 ) then
				
					val <= C0_4;
				else
				
					val <= val + C1_4;
				end if;
			else
				
				i <= i + C1_24;
			end if;
		end if;
	end process;
end XS40_ARCH;