--**************************************************************************--
-- clkdiv
--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity clkdiv is 
	port(rst : in STD_LOGIC;
             clk : in STD_LOGIC;
             slowclk : out STD_LOGIC);
end clkdiv;

--**************************************************************************--

architecture arch of clkdiv is

	constant C0_24 : UNSIGNED (23 downto 0) := "000000000000000000000000";
	constant C1_24 : UNSIGNED (23 downto 0) := "000000000000000000000001";
	constant CM_24 : UNSIGNED (23 downto 0) := "101101110001101100000000";
		
	signal tempslowclk : STD_LOGIC;
	signal i : UNSIGNED (23 downto 0);
begin	
	process(rst, clk)
	begin
		if( rst = '0' ) then

			i <= C0_24;
			slowclk <= '0';
			tempslowclk <= '0';
				
		elsif( clk'event and clk = '1' ) then

			if( i = CM_24 ) then
			
				i <= C0_24;
				slowclk <= not tempslowclk;
				tempslowclk <= not tempslowclk;
			else
				
				i <= i + C1_24;
			end if;
		end if;
	end process;
end arch;




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