Benchmark 3 Case Study

Design benchmarks were used to formally evaluate the RASSP process improvements. This report describes the third of four benchmarks (Benchmark 3) for the RASSP program. The complete hardware/software signal processor upgrade development originally planned for Benchmark 3 was not completed after a decision by the Navy not to use the original signal processor and the project was retarget to embedding a Navy sonar algorithm on Commercial-Off-The-Shelf (COTS) hardware. Nevertheless, several components of the RASSP process were exercised, a 2.3X overall reduction in time-to-market and a 2.9X reduction in development cost compared to traditional developments was demonstrated for the design of the FPCTL SEM-E (E-format standard electronic module) module and related board support package software. On the redirected part of the benchmark, 3.5X reduced real-time application software development time and development cost decreased by 7X was demonstrated through the use of the RASSP auto coding tool suite.

The focus of this part of the benchmark was an insertion of advanced technology into an existing Navy signal processor, the UYS-2A. The Navy (PMO-428 and PMA-299) and DARPA (ETO and ITO) jointly sponsored this program. The benchmark included technology from DARPA-ITO's High Performance Scalable Computing (HPSC) program and DARPA-ETO's RASSP program. The primary Navy project goal was to provide state of the art performance upgrade for the UYS-2A while retaining all hardware and software interfaces to the existing AN/UYS-2A signal processor to be used with the Airborne Low Frequency dipping SONAR (ALFS) being developed for the SH-60R helicopter.

On the UYS-2A signal-processor upgrade program, the FPCTL module design phase took only 13 weeks to complete, a 3X improvement compared to standard practice. The design included development of a module with multiple high-speed asynchronous buses and interfaces, complex FPGA and PLD designs, tight module layout, and design of assembly fixtures. The virtual prototype of the system enabled a disciplined design, and the integration of the 30,000 lines of board support package software proceeded at record speed because of the earlier hardware/software co-simulation. The necessity to use a state-of-the-art fine line printed circuit board (PCB) process that ended up taking 16 weeks (12 weeks greater then standard practice) to fabricate contributed to only reaching a 2.3X reduction in overall schedule.

Following the Navy's decision to use COTS based signal processor instead of the UYS-2A hardware for the production version of ALFS, Benchmark 3 was redirected to demonstrate RASSP autocoding of the Navy's shallow water active sonar processing algorithm. This algorithm called the Echo Tracking Classifier (ETC) was captured using a new RASSP autocoding tool called GEDAE™, so that the algorithm can be easily ported to several different commercial hardware products. The final Navy production target is yet to be finalized, but for this demonstration the ETC software was ported onto Mercury Power PC hardware.

On the ETC for ALFS algorithms on COTS hardware programover fifty thousand lines of legacy software was converted into GEDAE™ data flow graphs in less than twelve weeks. Mapping of the algorithm and optimization on the Mercury Computer DSP hardware took about two weeks. This gives 3.5X time improvement for real-time application development versus standard practice.