RASSP Design For Testability Application Note

The RASSP DFT insertion methodology is demonstrated by application to all phases of one of the RASSP Benchmark 3 benchmark projects (Benchmark 3). Using systems fabricated from today's high density packaging systems which compress functionality at the expense of accessibility, the BM3 application illustrates how DFT inserts full life cycle (i.e., system design to field deployment) testability. Also examined are systems fabricated using current high density packaging systems which compress functionality at the expense of accessibility. The economic benefits of DFT are also examined across the project life cycle and potential for life cycle cost (LCC) reduction is examined.

The system engineer applies the DFT methodology to develop unambiguous, quantifiable requirements. Assistance is also provided in the process of architecture trade off and selection. Testability insertion begins as consolidated requirements are developed by an integrated expert team representing design, manufacturing and field engineering project phases. The collaborative approach ensures that no single project phase is emphasized at the cost of another and that the end system will be optimized for testability throughout its life cycle. Received customer requirements are examined to ensure that they are consistent, realizable and valid. Test means for requirements verification are examined and a singular test philosophy (STP) is developed. That maximizes the effectiveness of the selected DFT approach over the product life cycle is maximized by using tests common to all life cycle phases is developed.

The design engineer verifies the operation and effectiveness of selected DFT features along with the functional system simulation. Component selection accompanies simulation to ensure that test circuitry can be integrated into the system hardware and software. IEEE 1149.1- and BIST (Built In Self Test) - enabled components and a complementary physical test bus architecture are added to board layouts. Test vectors are generated to be applied to DFT elements added to a design. Board level BIST technology is added to extend test coverage. A full set of test procedures is developed to meet the needs of development, manufacturing and deployment testing of the hardware.

RASSP DFT is supported with an extensive toolset and reusable templates supporting DFT during all the RASSP life cycle phases. Consolidated requirements are template based to ensure completeness. Test Strategy Diagrams (TSDs) implemented as EXCEL spreadsheets derived from the consolidated requirements distribute the requirements to lower packaging levels and support enforcement of requirements. A complete test architecture developed in parallel with the TSDs supplies a full set of test plans and procedures which measure compliance to requirements. A complete set of VHDL-based simulation and test vector generation tools supports development of JTAG--based tests and installation of board level BIST which maximizes hardware testability during manufacturing and field deployment. Any required supplementary ATE (Automatic Test Equipment) testing is also supported by definition of critical test points not covered by JTAG or BIST testing.