Lockheed Martin
Advanced Technology Laboratories






Rapid Prototyping of Application-Specific Signal Processors (RASSP)



CAD SYSTEM DESCRIPTION


BASELINE 2.0
CDRL A007
Contract Number: DAAL01-93-C-3380



June 1998





Submitted By:


Lockheed Martin RASSP Team
Lockheed Martin Advanced Technology Laboratories
Building A&E 2W
1 Federal Street
Camden, NJ 08102

For further information contact:
Mr. Dennis Basara
Telephone: 609-338-2545
Fax: 609-338-4155
E-mail: dbasara@atl.lmco.com



June 1998

TABLE OF CONTENTS
1.0 Introduction 1-1
1.1 RASSP Baseline 2 CAD System Overview 1-1
1.1.1 System Design Tools (System Definition) 1-2
1.1.2 Hardware/Software Co-Design CAE Tools (Architecture Definition Process) 1-2
1.1.3 Hardware Design Tools 1-3
1.1.4 Design-For-Test Tools 1-4
1.1.5 Enterprise System Tools 1-6
1.2

 

 Hardware for CAD Environment 1-7

 
2.0 Systems Design Tools 2-1
2.1 Process Summary 2-1
2.2 4 Systems Design CAE Tools 2-1
2.2.1 Marconi Systems 2-2
2.2.1.1 RTM 2-2
2.2.2 Ascent Logic 2-4
2.2.2.1 RDD-100 2-4
2.2.3 Alta Group 2-7
2.2.3.1 BONeS 2-7
2.2.3.2 Signal Processing Worksystem (SPW) 2-7
2.2.4 Mathworks 2-7
2.2.4.1 MATLAB 2-7
2.2.5 MSI 2-8
2.2.5.1 RAM/ILS 2-8
2.2.6 Lockheed Martin ATL 2-9
2.2.6.1 GEDAE™ 2-9
2.2.6.2 PRICE S/M/H/HL 2-10
2.2.7 Aspect Development 2-11
2.2.7.1 Explore (CLMS) 2-11
2.2.8 Interleaf 2-11
2.2.8.1 Technical Publishing Software (TPS) 2-11
2.3 System Design Tool Integration 2-12
2.3.1 RDD-100/PRICE/RAM-ILS Integration (RASSP Developed) 2-12
2.3.2 RTM/RDD-100 (Developed on LM EPI Program) 2-13
2.3.3

 

 RDD-100 BONeS (Developed on LM EPI Program 2-14
3.0 Hardware/Software Co-Design Tools 3-1
3.1 Process Summary 3-1
3.2 Hardware/Software Co-Design CAE Tools 3-3
3.2.1 JRS Research Laboratories 3-4
3.2.1.1 NetSyn 3-4
3.2.2 Savantage, Inc. 3-4
3.2.2.1 SavanSys 3-4
3.2.3 BDTI/UC Berkeley 3-5
3.2.3.1 Ptolemy 3-5
3.2.4 Lockheed Martin ATL 3-5
3.2.4.1 GEDAE™ 3-5
3.2.4.2 Application Interface Builder (AIB) 3-6
3.2.4.3 PRICE 3-6
3.2.5 Omniview/Honeywell 3-7
3.2.5.1 Performance Modeling Workbench (PMW) 3-7
3.2.6 Management Sciences Inc. 3-7
3.2.6.1 RAM-ILS 3-7
3.2.7 Marconi Systems 3-7
3.2.7.1 RTM 3-7
3.2.8 Alta Group 3-7
3.2.8.1 SPW 3-7
3.2.9 Mathworks 3-8
3.2.9.1 MATLAB 3-8
3.2.10 Precedence 3-8
3.2.10.1 SimMatrix 3-8
3.2.11 Mentor Graphics 3-8
3.2.11.1 QuickVHDL 3-8
3.2.12 MCCI 3-8
3.2.12.1 Autocoding Toolset 3-8
3.2.13 VERILOG 3-8
3.2.13.1 ObjectGEODE 3-8
3.2.14 Applied Dynamics International (ADI) 3-9
3.2.14.1 BEACON 3-9
3.2.15 Harris Electronic Design Automation 3-9
3.2.15.1 Harris EDAnavigator 3-9
3.2.16 Lucent 3-9
3.2.16.1 SPEAR 3-9
3.2.17 University Of Oregon 3-9
3.2.17.1 PIE (Performance Instrumentation Environment) 3-9
3.2.18 Ascent Logic 3-10
3.2.18.1

 

 RDD-100 3-10
4.0 Hardware Design Tools 4-1
4.1 Hardware Design Process Summary 4-1
4.2 Hardware Design CAE Tools 4-3
4.2.1 Mentor Graphics 4-4
4.2.1.1 Design Architect 4-4
4.2.1.2 QuickVHDL 4-6
4.2.1.3 Library Management System (LMS) 4-7
4.2.1.4 PLD Synthesis II 4-7
4.2.1.5 QuickPath 4-8
4.2.1.6 Board Designer 4-8
4.2.1.7 AutoTherm 4-10
4.2.1.8 MCM Station 4-10
4.2.2 Synopsys 4-10
4.2.2.1 VHDL Compiler 4-10
4.2.2.2 Design Compiler 4-10
4.2.2.3 DesignWare 4-11
4.2.2.4 SmartModel Library (Logic Modeling Group) 4-11
4.2.2.5 LM Family Hardware Modeler 4-11
4.2.2.6 VHDL Models (SourceModels) 4-13
4.2.3 NeoCAD 4-14
4.2.3.1 FPGA Foundry 4-14
4.2.4 Summit 4-14
4.2.4.1 TDS (Test Development Series) 4-14
4.2.4.2 Visual HDL 4-15
4.2.5 Precedence 4-15
4.2.5.1 SimMatrix 4-15
4.2.6 SDRC 4-15
4.2.6.1 Master Modeler 4-15
4.2.6.2 Sheet Metal Design 4-16
4.2.6.3 Drafting 4-16
4.2.6.4 Tolerance Analysis 4-16
4.2.6.5 Mechanism Design 4-16
4.2.6.6 View and Markup 4-16
4.2.6.7 Finite Element Modeling 4-16
4.2.6.8 Optimization 4-16
4.2.6.9 System Dynamics Analysis 4-17
4.2.7 Quickturn 4-17
4.2.7.1 System Realizer Family 4-17
4.2.8 VEDA Design Automation, Inc. 4-17
4.2.8.1 VHDLCover 4-17
4.2.9 Teradyne 4-17
4.2.9.1 VICTORY 4-17
4.2.10 Ascent Logic 4-18
4.2.10.1 RDD-100 4-18
4.2.11 Savantage 4-18
4.2.11.1 SavanSys 4-18
4.3 Hardware Design Tool Integration 4-18
4.3.1 Framework (Mentor's FALCON) 4-18
4.3.1.1 Common User Interface 4-19
4.3.1.2 Design Manager 4-19
4.3.1.3 BOLD Browser 4-19
4.3.1.4 Notepad 4-19
4.3.1.5 Decision Support System (DSS) 4-19
4.3.1.6

 

 AMPLE 4-19
5.0 Design-For-Test Tools 5-1
5.1 Process Description 5-1
5.2 Design-For-Test CAE Tools 5-3
5.2.1 Teradyne 5-4
5.2.1.1 VICTORY 5-4
5.2.1.2 LASAR 5-5
5.2.2 Naval Undersea Warfare Center 5-5
5.2.2.1 WSTA (Weapon System Testability Analyzer) 5-5
5.2.3 Detex Systems, Inc. 5-9
5.2.3.1 STAT (System Testability Analysis Tool) 5-9
5.2.4 Logic Vision Software 5-10
5.2.4.1 ASIC Test Tool Suite 5-10
5.2.5 Lockheed Martin ATL/Self Test Services 5-12
5.2.5.1 Test Strategy Diagram 5-12
5.2.6 ASSET, Inc. 5-15
5.2.6.1 ASSET Diagnostic System 5-15
5.2.7 Mentor/Teradyne 5-16
5.2.7.1 Virtual Test Manager: Testpoint Optimizer Software (VTM:TOP) 5-16
5.2.8 Rome Laboratory 5-17
5.2.8.1 TSTB WAVEs 5-17
5.2.9 Summit 5-17
5.2.9.1 TDS (Test Development Series) 5-17
5.2.10 Mentor 5-18
5.2.10.1 FASTSCAN 5-18
5.2.10.2 QuickGrade 5-18
5.2.10.3 PTM:SITE 5-18
5.2.11 National Semiconductor 5-18
5.2.11.1 SCANease 5-18
5.2.12 Synopsys 5-18
5.2.12.1 Test Compiler 5-18
5.2.13 MSI Systems 5-19
5.2.13.1 STARS (Formerly DARTS) 5-19
5.2.14 Test Economic Services 5-20
5.2.14.1 Economic Modeling Tools 5-20
5.2.15 IKOS 5-20
5.2.15.1 Voyager FS 5-20
5.2.16 ZYCAD 5-20
5.2.16.1

 

 Fault Simulation Accelerator 5-20
6.0 Enterprise System Tools 6-1
6.1 Enterprise System Overview 6-1
6.2 Enterprise System Tools 6-1
6.2.1 Intergraph 6-2
6.2.1.1 Design Methodology Manager 6-2
6.2.1.2 Asset and Information Management (AIM) 6-3
6.2.2 Aspect 6-6
6.2.2.1 Explore (CLMS) 6-6
6.2.3 Sandpiper Software, Inc. 6-9
6.2.3.1 RASSP Reuse Data Manager (RRDM) 6-9
6.2.4 TriTeal 6-11
6.2.4.1 TriTeal Enterprise Desktop (TED) 6-11
6.2.5 SCRA 6-12
6.2.5.1 Manufacturing Interface 6-12
6.2.6 Insoft 6-13
6.2.6.1 Communiqué and Cooltalk 6-13
6.2.7 Netscape 6-15
6.2.7.1 Netscape Enterprise Server 6-15
6.2.8 Viacrypt 6-15
6.2.8.1 Pretty Good Privacy (PGP) 6-15
6.2.9 Mentor 6-15
6.2.9.1 WorkExpert 6-15
6.2.10 KBSI 6-17
6.2.10.1 ProSim 6-17
6.2.11 AT&T 6-18
6.2.11.1 WITNESS 6-18
6.2.12 Microsoft 6-18
6.2.12.1

 

 MS Project 6-18
Appendix 1 RASSP Baseline 2.0 CAD System Tools A-1
  System Design A-1
  Hardware/Software Co-Design A-1
  Hardware Design A-2
  Design-For-Test A-3
  Enterprise System A-4

 

LIST OF ILLUSTRATIONS
1.1-1 RASSP Design Environment Baseline 2 1-1

 

    
2.2-1 RASSP Baseline 2 system design tools 2-2
2.2-2 RTM lifecycle support 2-3
2.2-3 RDD-100 supports requirements and functional analysis 2-5
2.2-4 Behavior diagram structures 2-6
2.3-1 RDD-100/PRICE/RAM-ILS integration 2-13
2.3-2 Overview of RTM/RDD-00 integration 2-14
2.3-3 Overview of RDD-100 BONeS integration 2-15

 

    
3.1-1 Software architecture 3-1
3.1-2 Architecture selection toolset 3-2
3.2-1 Application Interface Builder bridges gap between data flow and

control flow

 3-6

 

    
4.1-1 RASSP hardware design tools 4-1
4.2-1 Mentor IDEA EDA tool set 4-5
4.2-2 Design architect screen 4-6
4.2-3 Board designer process flow 4-9
4.2-4 LM Family usage in the design cycle 4-12
4.3-1 FALCON Framework components 4-18

 

    
5.2-1 WSTA role in IDSS 5-6
5.2-2 WSTA functional flow diagram 5-6
5.2-3 ASICTEST tool suite 5-11
5.2-4 Test strategy diagram concept 5-13
5.2-5 Hierarchy of test strategy diagrams 5-14
5.2-6 Typical requirements TSD 5-15

 

    
6.2-1 Search results screen 6-8
6.2-2 Sandpiper Software Intelligent Information Broker Context 6-10
6.2-3

RASSP manufacturing interface architecture

 6-13
6.2-4

Supporting electronic commerce

 6-14

LIST OF TABLES
2.2-1 RAM/ILS tool features 2-8

 

    
5-1 DFT Tool Gap 5-1