Design menu

Model Technology Inc.

Design menu

Browse Libraries

browse all libraries within the scope of the design; see also "Managing library contents"

Create a New Library

create a new library or map a library to a new name; see "Creating a library"

Import Library

import FPGA libraries; see "Importing FPGA libraries" for details

Compile

compile HDL source files into the current project's work library

Load Design

initiate simulation by specifying the top level design unit in the Design tab; specify HDL specific simulator settings with the VHDL and Verilog tabs; specify the library to search for design units instantiated from Verilog with the Libraries tab; specify settings relating to the annotation of design timing with the SDF tab

End Simulation

end the simulation (returns to the ModelSim command line)

Browse Libraries	browse all libraries within the scope of the design; see also "Managing library contents"
Create a New Library	create a new library or map a library to a new name; see "Creating a library"
Import Library	import FPGA libraries; see "Importing FPGA libraries" for details
Compile	compile HDL source files into the current project's work library
Load Design	initiate simulation by specifying the top level design unit in the Design tab; specify HDL specific simulator settings with the VHDL and Verilog tabs; specify the library to search for design units instantiated from Verilog with the Libraries tab; specify settings relating to the annotation of design timing with the SDF tab
End Simulation	end the simulation (returns to the ModelSim command line)

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