mti_NextProcess()

Gets the next VHDL process in a region.

Syntax

process_id = mti_NextProcess() 

Returns

Name	Type	Description
process_id	mtiProcessIdT	A handle to the next VHDL process in the current region

Arguments

None

Description

mti_NextProcess() returns a handle to the next process in the region set by the latest call to mti_FirstProcess(). mti_NextProcess() returns NULL if there are no more processes.

Related functions

mti_FirstProcess()

Example

FLI code

#include <mti.h>

void printProcesses( mtiRegionIdT region, int indent )
{
  mtiProcessIdT procid;

  for ( procid = mti_FirstProcess( region ); procid;
        procid = mti_NextProcess() ) {
    if ( procid ) {
      mti_PrintFormatted( "%*cProcess %s\n", indent, ' ',
                         mti_GetProcessName( procid ) );
    }
  }
}

void printHierarchy( mtiRegionIdT region, int indent )
{
  char *       region_name;
  mtiRegionIdT regid;

  region_name = mti_GetRegionFullName( region );
  mti_PrintFormatted( "%*cRegion %s\n", indent, ' ', region_name );
  indent += 2;
  printProcesses( region, indent );
  for ( regid = mti_FirstLowerRegion( region );
        regid; regid = mti_NextRegion( regid ) ) {
    printHierarchy( regid, indent );
  }
  mti_VsimFree( region_name );
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nHierarchy:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
begin
  b <= a after delay;

  p1 : process
    variable count : integer := 0;
  begin
    count := count + 1;
    wait on a;
  end process;
end b;

entity mid is
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

component inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end component;

begin

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;
  s3 <= not s3 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a;

entity top is
end top;

architecture a of top is
  component mid is
end component;
begin
  inst1 : mid;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Hierarchy:
#  Region /top
#    Region /top/inst1
#      Process line__58
#      Process line__57
#      Region /top/inst1/flip
#        Process p1
#        Process line__19
#      Region /top/inst1/i1
#      Region /top/inst1/toggle
#        Process p1
#        Process line__19
VSIM 1> quit 

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