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mti_GetVarType()
Gets the type of a VHDL variable.
Syntax
type_id = mti_GetVarType( variable_id )Returns
Name Type Description type_id mtiTypeIdT A handle to the type ID of the specified variableArguments
Name Type Description variable_id mtiVariableIdT A handle to a VHDL variableDescription
mti_GetVarType() returns a handle to the type of the specified VHDL variable.
Related functions
Example
FLI code
#include <mti.h> static char * getTypeStr( mtiTypeIdT typeid ) { char * typestr; switch ( mti_GetTypeKind( typeid ) ) { case MTI_TYPE_SCALAR: typestr = "Scalar"; break; case MTI_TYPE_ARRAY: typestr = "Array"; break; case MTI_TYPE_RECORD: typestr = "Record"; break; case MTI_TYPE_ENUM: typestr = "Enum"; break; case MTI_TYPE_PHYSICAL: typestr = "Physical"; break; case MTI_TYPE_REAL: typestr = "Real"; break; case MTI_TYPE_ACCESS: typestr = "Access"; break; case MTI_TYPE_FILE: typestr = "File"; break; case MTI_TYPE_TIME: typestr = "Time"; break; default: typestr = "UNKNOWN"; break; } return typestr; } static void printVarInfo( mtiVariableIdT varid ) { mti_PrintFormatted( "Variable %12s is of type %s\n", mti_GetVarName( varid ), getTypeStr( mti_GetVarType( varid ))); } static void initInstance( void ) { mtiProcessIdT procid; mtiRegionIdT regid; mtiVariableIdT varid; regid = mti_GetTopRegion(); for ( procid = mti_FirstProcess( regid ); procid; procid = mti_NextProcess() ) { for ( varid = mti_FirstVar( procid ); varid; varid = mti_NextVar() ) { printVarInfo( varid ); } } } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { mti_AddLoadDoneCB( initInstance, 0 );}HDL code
entity for_model is end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl;"; begin end a; library ieee; use ieee.std_logic_1164.all; entity top is type bitarray is array( 3 downto 0 ) of bit; type rectype is record a : real; b : std_logic; c : bitarray; end record; end top; architecture a of top is component for_model end component; for all : for_model use entity work.for_model(a); begin inst1 : for_model; p1 : process variable bitsig : bit := '1'; variable intsig : integer := 21; variable realsig : real := 16.35; variable timesig : time := 5 ns; variable stdlogicsig : std_logic := 'H'; variable bitarr : bitarray := "0110"; variable stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH"; variable rec : rectype := ( 1.2, '0', "1001" ); begin bitsig := not bitsig; intsig := intsig + 1; realsig := realsig + 1.1; timesig := timesig + 1 ns; stdlogicsig := not stdlogicsig; bitarr := not bitarr; stdlogicarr := not stdlogicarr; rec.a := rec.a + 1.1; rec.b := not rec.b; rec.c := not rec.c; wait for 5 ns; end process; end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading .../modeltech/sunos5/../ieee.std_logic_1164(body) # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl # Variable bitsig is of type Enum # Variable intsig is of type Scalar # Variable realsig is of type Real # Variable timesig is of type Time # Variable stdlogicsig is of type Enum # Variable bitarr is of type Array # Variable stdlogicarr is of type Array # Variable rec is of type Record VSIM 1> quit
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