mti_GetVarName()

Gets the simple name of a VHDL variable.

Syntax

var_name = mti_GetVarName( variable_id ) 

Returns

Name	Type	Description
var_name	char *	The simple name of the specified variable

Arguments

Name	Type	Description
variable_id	mtiVariableIdT	A handle to a VHDL variable

Description

mti_GetVarName() returns the simple name of the specified VHDL variable or NULL if no information can be found. The returned pointer must not be freed.

mti_GetVarName() cannot be used with variable IDs passed as foreign subprogram parameters.

Related functions

None

Example

FLI code

#include <stdio.h>
#include <mti.h>

#define NAME_MAX 1024

typedef struct varInfoT_tag {
  struct varInfoT_tag  * next;
  char                 * name;
  mtiProcessIdT          procid;
  mtiRegionIdT           regid;
  mtiTypeIdT             typeid;
  mtiVariableIdT         varid;
} varInfoT;

typedef struct {
  varInfoT      * var_info;     /* List of variables. */
  mtiProcessIdT   proc;         /* Test process id. */
} instanceInfoT;

static void checkValues( void *inst_info )
{
 char          * region_name;
 char            var_name[NAME_MAX];
 instanceInfoT * inst_data = (instanceInfoT *)inst_info;
 varInfoT      * varinfo;

 mti_PrintFormatted( "Time [%d,%d]:\n", mti_NowUpper(), mti_Now() );

 for ( varinfo = inst_data->var_info; varinfo; varinfo = varinfo->next ) {
  region_name = mti_GetRegionFullName( varinfo->regid );
  sprintf( var_name, "%s/%s/%s", region_name,
          mti_GetProcessName( varinfo->procid ), varinfo->name );
  mti_PrintFormatted( "  Variable %s = %s\n",
                   var_name, mti_GetVarImageById( varinfo->varid ));
  mti_VsimFree( region_name );
 }

 mti_ScheduleWakeup( inst_data->proc, 5 );
}

static varInfoT * setupVariable(
  mtiVariableIdT varid,
  mtiRegionIdT   regid,
  mtiProcessIdT  procid
)
{
  varInfoT * varinfo;

  varinfo         = (varInfoT *) mti_Malloc( sizeof(varInfoT) );
  varinfo->varid  = varid;
  varinfo->name   = mti_GetVarName( varid );
  varinfo->typeid = mti_GetVarType( varid );
  varinfo->regid  = regid;
  varinfo->procid = procid;
  varinfo->next   = 0;

  return( varinfo );
}

static void initInstance( void )
{
  instanceInfoT * inst_data;
  mtiProcessIdT   procid;
  mtiRegionIdT    regid;
  mtiVariableIdT  varid;
  varInfoT      * curr_info;
  varInfoT      * varinfo;

  inst_data           = mti_Malloc( sizeof(instanceInfoT) );
  inst_data->var_info = 0;

  regid = mti_GetTopRegion();
  for ( procid = mti_FirstProcess( regid );
        procid; procid = mti_NextProcess() ) {
    for ( varid = mti_FirstVar( procid ); varid; varid = mti_NextVar() ) {
      varinfo = setupVariable( varid, regid, procid );
      if ( inst_data->var_info == 0 ) {
        inst_data->var_info = varinfo;
      }
      else {
        curr_info->next = varinfo;
      }
      curr_info = varinfo;
    }
  }

  inst_data->proc = mti_CreateProcess( "Test Process", checkValues,
                                      (void *)inst_data );
  mti_ScheduleWakeup( inst_data->proc, 4 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is

  type bitarray  is array( 3 downto 0 ) of bit;
  type intarray  is array( 1 to 3 )     of integer;
  type realarray is array( 1 to 2 )     of real;
  type timearray is array( -1 to 0 )    of time;

  type rectype is record
    a : real;
    b : std_logic;
    c : bitarray;
  end record;

end top;

architecture a of top is

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

  p1 : process

    variable bitsig      : bit       := '1';
    variable intsig      : integer   := 21;
    variable realsig     : real      := 16.35;
    variable timesig     : time      := 5 ns;
    variable stdlogicsig : std_logic := 'H';

    variable bitarr      : bitarray  := "0110";
    variable stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH";
    variable intarr      : intarray  := ( 10, 11, 12 );
    variable realarr     : realarray := ( 11.6, 101.22 );
    variable timearr     : timearray := ( 15 ns, 6 ns );

    variable rec         : rectype   := ( 1.2, '0', "1001" );

  begin

    bitsig      := not bitsig;
    intsig      := intsig + 1;
    realsig     := realsig + 1.1;
    timesig     := timesig + 1 ns;
    stdlogicsig := not stdlogicsig;

    bitarr      := not bitarr;
    stdlogicarr := not stdlogicarr;

    intarr(1)   := intarr(1) + 1;
    intarr(2)   := intarr(2) + 1;
    intarr(3)   := intarr(3) + 1;

    realarr(1)  := realarr(1) + 1.1;
    realarr(2)  := realarr(2) + 1.1;

    timearr(-1) := timearr(-1) + 1 ns;
    timearr(0)  := timearr(0) + 1 ns;

    rec.a       := rec.a + 1.1;
    rec.b       := not rec.b;
    rec.c       := not rec.c;

    wait for 5 ns;

  end process;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 12
# Time [0,4]:
#   Variable /top/p1/bitsig = '0'
#   Variable /top/p1/intsig = 22
#   Variable /top/p1/realsig = 17.45
#   Variable /top/p1/timesig = 6 ns
#   Variable /top/p1/stdlogicsig = '0'
#   Variable /top/p1/bitarr = "1001"
#   Variable /top/p1/stdlogicarr = "1010"
#   Variable /top/p1/intarr = {11} {12} {13}
#   Variable /top/p1/realarr = {12.7} {102.32}
#   Variable /top/p1/timearr = {16 ns} {7 ns}
#   Variable /top/p1/rec = {2.3} {'1'} {"0110"}
# Time [0,9]:
#   Variable /top/p1/bitsig = '1'
#   Variable /top/p1/intsig = 23
#   Variable /top/p1/realsig = 18.55
#   Variable /top/p1/timesig = 7 ns
#   Variable /top/p1/stdlogicsig = '1'
#   Variable /top/p1/bitarr = "0110"
#   Variable /top/p1/stdlogicarr = "0101"
#   Variable /top/p1/intarr = {12} {13} {14}
#   Variable /top/p1/realarr = {13.8} {103.42}
#   Variable /top/p1/timearr = {17 ns} {8 ns}
#   Variable /top/p1/rec = {3.4} {'0'} {"1001"}
VSIM 2> quit 

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