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mti_Command()
Syntax
mti_Command( command )Returns
Arguments
Name Type Description command char * A simulator commandDescription
mti_Command() causes the specified command to be executed by the simulator. The string must contain the command just as it would be typed at the VSIM prompt. The results of the command are transcribed in the vsim transcript.
Any command that changes the state of simulation (such as run, restart, restore, etc.) cannot be sent from a foreign architecture, foreign subprogram, or callback that is executing under the direct control of vsim.
Related functions
Example
FLI code
#include <stdio.h> #include <stdlib.h> #include <mti.h> typedef enum { STD_LOGIC_U, /* 'U' */ STD_LOGIC_X, /* 'X' */ STD_LOGIC_0, /* '0' */ STD_LOGIC_1, /* '1' */ STD_LOGIC_Z, /* 'Z' */ STD_LOGIC_W, /* 'W' */ STD_LOGIC_L, /* 'L' */ STD_LOGIC_H, /* 'H' */ STD_LOGIC_D /* '-' */ } StdLogicT; void monitorSignal( void * param ) { char buffer[256]; char * region_name; char * signal_name; mtiSignalIdT sigid = (mtiSignalIdT)param; switch ( mti_GetSignalValue( sigid ) ) { case STD_LOGIC_X: case STD_LOGIC_W: signal_name = mti_GetSignalName( sigid ); region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid )); mti_PrintFormatted( "Time [%d,%d] delta %d: Signal %s/%s is UNKNOWN\n", mti_NowUpper(), mti_Now(), mti_Delta(), region_name, signal_name ); sprintf( buffer, "drivers %s/%s", region_name, signal_name ); mti_Command( buffer ); mti_VsimFree( region_name ); break; default: break; } } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { mtiProcessIdT procid; mtiSignalIdT sigid; sigid = mti_FindSignal( "/top/s1" ); procid = mti_CreateProcess( "SignalMonitor", monitorSignal, sigid ); mti_Sensitize( procid, sigid, MTI_EVENT ); }HDL code
library ieee; use ieee.std_logic_1164.all; entity top is end top; architecture a of top is signal s1 : std_logic := '0'; begin p1 : process begin c1 : case s1 is when 'U' => s1 <= 'X' after 5 ns; when 'X' => s1 <= '0' after 5 ns; when '0' => s1 <= '1' after 5 ns; when '1' => s1 <= 'Z' after 5 ns; when 'Z' => s1 <= 'W' after 5 ns; when 'W' => s1 <= 'L' after 5 ns; when 'L' => s1 <= 'H' after 5 ns; when 'H' => s1 <= '-' after 5 ns; when '-' => s1 <= 'U' after 5 ns; end case c1; wait for 5 ns; end process; end a;Simulation output
% vsim -c top -foreign "initForeign for_model.sl" Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -foreign {initForeign for_model.sl} -c top # Loading .../modeltech/sunos5/../std.standard # Loading .../modeltech/sunos5/../ieee.std_logic_1164(body) # Loading work.top(a) # Loading ./for_model.sl VSIM 1> run 50 # Time [0,15] delta 0: Signal /top/s1 is UNKNOWN # Drivers for /top/s1: # W : Signal /top/s1 # W : Driver /top/p1 # # Time [0,40] delta 0: Signal /top/s1 is UNKNOWN # Drivers for /top/s1: # X : Signal /top/s1 # X : Driver /top/p1 # VSIM 2> quit
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