Keyword: PROCESS
The process keyword defines a sequential process intended to model all or part of a design entity.
A process statement includes—in this order—an optional sensitivity list, a declarations section, a "begin" statement, the sequential statements describing the operation of the process, and an "end" statement.
The sensitivity list identifies signals to which the process is sensitive. Whenever an event occurs on an item in the sensitivity list, the sequential instructions in the process are executed. If no sensitivity list is provided, the process executes until suspended by a wait statement.
In addition to signal and variable assignments, the sequential statements in the body of the process can include the following: assertion, case, exit, if, loop, next, null, procedure, return, and wait.
Example
reg: process(Rst,Clk)
variable Qreg: std_ulogic_vector(0 to 7);
begin
if Rst = '1' then -- Async reset
Qreg := "00000000";
elsif rising_edge(Clk) then
if Load = '1' then
Qreg := Data;
else
Qreg := Qreg(1 to 7) & Qreg(0);
end if;
end if;
Q <= Qreg;
end process;
LRM
9.2
See also
