Example: Parity
Xor.VHD
-------------------------------------------------------
-- Entity: XOR
--
Library ieee;
Use ieee.std_logic_1164.all;
Entity XOR2 Is
Port (
A: in std_ulogic;
B: in std_ulogic;
Y: out std_ulogic
);
End XOR2;
Architecture XOR_A of XOR2 Is
Begin
Y <= A xor B;
End XOR_A;
Parity.VHD
--------------------------------------------------
-- Parity generator.
--
-- This example demonstrates the use of generate
-- statements. The parity generation circuit is built
-- from a chain of exclusive-OR gates, which have been
-- defined separately. (A tree of XOR gates is, of
-- course, a more efficient/faster solution for parity
-- generation.)
--
-- Copyright 1995, Accolade Design Automation, Inc.
--
library ieee;
use ieee.std_logic_1164.all;
entity parity10 is
port(D: in std_ulogic_vector(0 to 9);
ODD: out std_ulogic);
constant WIDTH: integer := 10;
end parity10;
library work;
use work.xor2;
architecture structure of parity10 is
component xor2
port(A,B: in std_ulogic;
Y: out std_ulogic);
end component;
signal p: std_ulogic_vector(0 to WIDTH - 2);
for all: xor2 use entity work.xor2(xor_a);
begin
-- The outermost generate loop is a for-generate loop
-- that repeats once for each of the XOR gates required
-- for the circuit...
G: for I in 0 to (WIDTH - 2) generate
-- This generate statement creates the first XOR gate
-- in the series...
G0: if I = 0 generate
X0: xor2 port map(A => D(0), B => D(1), Y => p(0));
end generate G0;
-- This generate statement creates the middle XOR gates
-- in the series...
G1: if I > 0 and I < (WIDTH - 2) generate
X0: xor2 port map(A => p(i-1), B => D(i+1), Y => p(i));
end generate G1;
-- This generate statement creates the last XOR gate
-- in the series...
G2: if I = (WIDTH - 2) generate
X0: xor2 port map(A => p(i-1), B => D(i+1), Y => ODD);
end generate G2;
end generate G;
end structure;
Testpar.VHD
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity testbnch is
end testbnch;
use work.all;
architecture behavior of testbnch is
component parity10
port(D: in std_ulogic_vector(0 to 9);
ODD: out std_ulogic);
end component;
signal D: std_ulogic_vector(0 to 9);
signal ODD: std_ulogic;
begin
DUT: parity10 port map (D,ODD);
process
begin
D <= "0000000001";
wait for 50 ns;
D <= "1000000001";
wait for 50 ns;
D <= "0100100001";
wait for 50 ns;
D <= "0000000011";
wait for 50 ns;
D <= "0100000000";
wait for 50 ns;
D <= "1010100010";
wait for 50 ns;
D <= "1111111101";
wait for 50 ns;
D <= "0111000001";
wait for 50 ns;
D <= "1000000000";
wait for 50 ns;
end process;
end behavior;