FLEX SBC09 System Registers
Processor DAT and Register MAP
On RESET, DAT RAM may be written to at the top 256 bytes of processor memory.
The top 4 Kbytes of MEM3 are also mapped at $F000 - $FFFF.
Write Only System Registers are mapped at $FE00 - $FE07.
$FFF0 - $FFFF
| User 15 DAT RAM
|
$FFE0 - $FFEF
| User 14 DAT RAM
|
.-
| -
|
$FF00 - $FF0F
| User 0 (System) DAT RAM
|
$FE00 - $FE07
| System Registers
|
Write Only System Registers:
$FE00 - External Bus Wait State and Clock Divider Register
-
| CLK2
| CLK1
| CLK0
| - | TWST2
| TWST1
| TWST0
|
$FE01 - User Mode Fuse Counter and User DAT select
UMF3
| UMF2
| UMF1
| UMF0
| UDS3
| UDS2
| UDS1
| UDS0
|
$FE02 - IO Select register
$FE03 - External Bus Select Register
A19
| A18
| A17
| A16
| MASK19
| MASK18
| MASK17
| MASK16
|
$FE04 - MEM0 Select register
A19
| A18
| A17
| A16
| MASK19
| MASK18
| MASK17
| MASK16
|
$FE05 - MEM1 Select register
A19
| A18
| A17
| A16
| MASK19
| MASK18
| MASK17
| MASK16
|
$FE06 - MEM2 Select register
A19
| A18
| A17
| A16
| MASK19
| MASK18
| MASK17
| MASK16
|
$FE07 - MEM3 Select register
A19
| A18
| A17
| A16
| MASK19
| MASK18
| MASK17
| MASK16
|
Programmable Chip Select :
Memory Chip selects MEM0 - MEM3 allow different size RAM, EPROM and Flash
to be mapped into Physical memory space. Chip sizes can be programmed from 64K to
1 Mbyte and may be mapped anywhere in the 1 Mbyte physical addressing range.
Each MEM select register has 4 Mask bit to define which address bits are qualified for
memory decoding. The top 4 bits of the memory select registers define the physical address
the memories will be mapped to.
The IO register page is restricted to 4KBytes to save space. All 8 bits of the IO select register
are used in defining the physical address. A 64K - 1Mbyte External window may be mapped
anywhere in the memory map to allow access to devices on the SS-50 bus.
The select registers will be prioritised so that address ranges can overlap. MEM0 has the lowest
priority, then MEM1, MEM2, MEM3, IO and EXTERNAL the highest. If any memory is not
decoded it is assumed to be external. This means you could have 2 x 512Kbyte RAM chips in
MEM0 and MEM1 sockets and still have 64Kbyte ROMs in say MEM2 and MEM3 overriding
the MEM0 and MEM1 chip selects.
On reset all chip select registers are cleared, but the top 4Kbytes of MEM3 will be mapped
into processor memory. DAT RAM output will be tristated and pulled high by pull up resistors
on PA19 - PA12. The reset routine must program the DAT and chip select register with
appropriate values to map RAM, ROM and IO as required. Writing a zero to the User DAT
select register should enable the DAT in User 0 or system mode.
DAT - Dynamic Address Translation
Processor address bits A15 - A12 are applied to the DAT RAM address bits TA0 - TA3
DAT RAM address bit TA4 - TA7 are connected to a User DAT select register.
The DAT RAM data bits PA19 - PA12 form the extended address lines, allowing any
4K segment of the physical address range to be mapped into the 64K logical address range
of the CPU.
The DAT is programmed by writing to the top 256 bytes of memory in the processor address
range when the board is in System or User 0 mode. There are 16 DAT banks of 16 bytes each.
The other DAT banks are accessed through the User DAT select register on entry to the User mode.
On reset, system mode is selected (User 0) and the 16 bytes from $FF00 - $FF0F are used.
Each byte of the DAT corresponds to the physical address segment to be mapped by the top 4 bits
of the processor address lines A15-A12.
User Mode Fuse Counter and User DAT Select.
The User DAT select and User Mode Fuse counter register selects the approriate DAT
configuration for a user process when entering user mode.
This register simply holds the top 4 bits of the DAT RAM (UDS3=TA7 - UDS0=TA4)
and a 4 bit preset value for the User Mode Fuse Counter. After the User DAT select
register has the user number written to it and a fuse count, the User Mode Fuse counter
counts down every subsequent E clock, until it reaches zero. It then latches the value in the
User DAT Select bits onto the high DAT address lines TA4 - TA7 and sets the System/User
Mode flag to User Mode, unless the User number is zero. User 0 is reseved for System mode.
The User Mode Fuse Counter is typically used with an RTI instruction to re-enter user space
from a system call. The Fuse count must be carefully selected such that the User bank is
selected when registers are restored from the stack as a result of the RTI.
When an interrupt acknowledge bus cycle occurs as a result of a software or hardware interrupt,
the System/User Mode flag is set to System and the User DAT Select register is cleared.
This will select the DAT setup for System mode and enable access to the DAT at the top of CPU
memory.
On reset, the System mode is selected, but the DAT will be disabled. A zero must be written to the
the user DAT select register to enable the DAT in System mode (User 0).
Wait State Generator and System Clock divider
The wait state generator stretches the E and Q clocks of the processor for slow external
bus devices. The wait state delay is ORed with the external wait state input (BMRDY)
to produce the processor MRDY input. Zero to 7 clock cycle delays may be inserted.
The top 3 bits of this register are used to select the processor clock divider ratio. The
master clock is 24MHz , so this must be divided down for the CPU clock.
This register is cleared on reset so the slowest processor clock is selected. Not that
the EXTAL frequency is 4 times the bus clock rate, so a 2MHz 6809 requires an 8MHz
EXTAL signal.
-
| CLK2
| CLK1
| CLK0
| Divisor
| EXTAL
|
0
| 0
| 0
| 0
| div 8
| 3MHz
|
0
| 0
| 0
| 1
| div 1
| 24MHz
|
0
| 0
| 1
| 0
| div 2
| 12MHz
|
0
| 0
| 1
| 1
| div 3
| 8MHz
|
0
| 1
| 0
| 0
| div 4
| 6MHz
|
0
| 1
| 0
| 1
| div 5
| 4.8 MHz
|
0
| 1
| 1
| 0
| div 6
| 4MHz
|
0
| 1
| 1
| 1
| div 7
| 3.4444 MHz
|