--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 12/21/98
-- Version 1.2
-- Notes: This file implements the BIOS device.  This device contains
--	  some program instructions that it loads into the main memory
--	  and asserts the ready signal.  Subsequently the processors
--	  can be activated when the ready signal is asserted and thus
--	  starting execution of the loaded program.
--	  
--

--*************************************************************************--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--*************************************************************************--

entity BIOS is
	port( clk  : in STD_LOGIC;
	      rst  : in STD_LOGIC;
	      data : out UNSIGNED(31 downto 0);
              addr : out UNSIGNED(22 downto 0);
              rd   : out STD_LOGIC;
              wr   : out STD_LOGIC;
	      rdy  : in STD_LOGIC;
	      cs   : out STD_LOGIC );
end BIOS;

--*************************************************************************--

architecture BHV_BIOS of BIOS is

	--
	-- type declarations
	--
	subtype MEM_CELL_TYPE is UNSIGNED(31 downto 0);
	type PROG_MEM_TYPE is array(0 to 30) of MEM_CELL_TYPE;
	type STATE_TYPE is (WRITE_S, WRITE2_S, DONE_S);

	--
	-- constant declarations
	--
	constant PROGRAM : PROG_MEM_TYPE := (	

		"00000000100000000000000010000000",  -- LI	R1, 128
		"00110000100000000000010000000111",  -- STORE	1031, R1
		"00000000100000000000000000000001",  -- LI	R1, 1
		"00110000100000000000001000000001",  -- STORE	R1, 513
		"00000011000000000000000000011111",  -- LI	R6, 31 (PICT)
		"00100001000000000000001000000000",  -- LOAD	R2, 512			:L2(5)
		"10110001100010000010000000000000",  -- EQ	R3, R2, R1
		"01010001100000000000000000001001",  -- JNZ	R3, 9(L1)
		"01110000000000000000000000000101",  -- JMP	5(L2)
		"00010001000000000000000000000000",  -- MOV	R2, R0			:L1(9)
		"00000001100000000000000100000000",  -- LI	R3, 256
		"00000011100000000000000000000010",  -- LI	R7, 2			:L6(11)
		"00000100000000000000000000000011",  -- LI	R8, 3
		"01000010000010000110000000000000",  -- GE	R4, R2, R3
		"01010010000000000000000000011110",  -- JNZ	R4, 30(L3)
		"00100010100000000000001000000010",  -- LOAD	R5, 514
		"00110011100000000000010000000011",  -- STORE	R7, 1027
		"00110010100000000000010000000000",  -- STORE	R5, 1024
		"00110100000000000000010000000011",  -- STORE	R8, 1027
		"00100100100000000000010000000010",  -- LOAD	R9, 1026		:L5(19)  
		"10110101001001000010000000000000",  -- EQ	R10, R9, R1
		"01010101000000000000000000010111",  -- JNZ	R10, 23(L4)
		"01110000000000000000000000010011",  -- JMP	19(L5)
		"00100101100000000000010000000001",  -- LOAD	R11, 1025		:L4(23)
		"11000101100110000000000000000000",  -- STOREI	R11, R6
		"00110101100000000000010000000100",  -- STORE	R11, 1028
		"00110101100000000000101110111000",  -- STORE	R11, 3000
		"01100011000110000010000000000000",  -- ADD	R6, R6, R1
		"01100001000010000010000000000000",  -- ADD	R2, R2, R1
		"01110000000000000000000000001011",  -- JMP	11(L6)
		"01110000000000000000000000011110"   -- JMP	30(L3)			:L3(30)
	);

	constant Z_32 : UNSIGNED(31 downto 0) := 
		"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

	constant Z_23 : UNSIGNED(22 downto 0) :=
		"ZZZZZZZZZZZZZZZZZZZZZZZ";

	constant C0_32 : UNSIGNED(31 downto 0) :=
		"00000000000000000000000000000000";

	constant C0_23 : UNSIGNED(22 downto 0) :=
		"00000000000000000000000";

	constant C1_23 : UNSIGNED(22 downto 0) :=
		"00000000000000000000001";

	constant PROG_SIZE : UNSIGNED(22 downto 0) :=
		"00000000000000000011111";

	signal loct  : UNSIGNED(22 downto 0);
	signal state : STATE_TYPE;

begin

	process(clk, rst)
	begin
		if( rst = '1' ) then

			--
			-- steady state
			--
			state <= WRITE_S;
			loct <= C0_23;
			data <= C0_32;
			addr <= C0_23;
			wr <= '0';
			rd <= '0';
			cs <= '0';

		elsif( clk'event and clk = '1' ) then

			--
			-- steady state
			--
			data <= C0_32;
			addr <= C0_23;
			rd <= '0';
			wr <= '0';
			cs <= '0';

			--
			-- otherwise
			--
			case( state ) is

				when WRITE_S =>
				
					state <= WRITE_S;
					if(loct = PROG_SIZE and rdy = '1') then

						state <= DONE_S;

					elsif( rdy = '1' ) then

						data <= 
                                                   PROGRAM(conv_integer(loct));
						addr <= loct;
						wr <= '1';
						loct <= loct + C1_23;
						state <= WRITE2_S;
					end if;
				
				when WRITE2_S =>
					state <= WRITE_S;

				when DONE_S =>
					data <= Z_32;
					addr <= Z_23;
					rd <= 'Z';
					wr <= 'Z';
					cs <= '1';
					state <= DONE_S;
			end case;
		end if;
	end process;
end BHV_BIOS;

--*************************************************************************--

configuration CFG_BIOS of BIOS is
	for BHV_BIOS
	end for;
end CFG_BIOS;

-- end of file --