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September 14, 1998, Issue: 1025 Section: News VLSI's tool puts system-chip design on fast track David Lammers
San Jose, Calif. - VLSI Technology Inc. is launching an ambitious counter to the growing design-productivity gap, a rapid silicon prototyping approach named Velocity. The tool is essentially a configurable board-level system-on-chip lab based on VLSI's intellectual property and software to help turn such a board design into a system chip. Rapid silicon prototyping, or RSP, attacks system-on-chip design from several approaches simultaneously, allowing hardware and software development to proceed in parallel. VLSI engineers have been using an internal version of the RSP development methodology since November 1995, but the company has not offered it externally until now. The first board will be used in the development of printer engines, data communications devices or domestic automation controllers. VLSI is in the process of developing other boards that could be used by engineers in the wireless, data communications and digital consumer fields. Velocity approaches configurable blocks of logic much in the manner of a compiler, said Bob Payne, who is in charge of strategic technologies at VLSI. "Everyone in the industry agrees that a radical shift in design methodology is required," said Payne. "We are ridiculously underutilizing the potential of the silicon, and something has to be done about it. We think that is what we have done, using the least abstract way to model silicon, which is to use silicon to model silicon." Limited by the bus Though analyst Rita Glover of EDA Today hailed the company as "forward thinking" and Velocity as "much needed," the initial version works only with VLSI's silicon and on-chip bus architectures. HDLi, or hardware description language integrator, is a tool for designing chips built with reusable blocks of logic. HDLi takes software descriptions of intellectual property (IP) and turns them into "objects" that can be handled by VLSI's on-chip bus offerings. A hierarchy of three on-chip buses creates standard interfaces between the IP blocks. Each of these blocks will include an on-block interface to one of the three buses, which simplifies the integration of blocks provided by commercial intellectual-property vendors. The buses include the standard ARM Ltd. AMBA system bus, the VLSI peripheral bus and an on-chip PCI bus. The boards are a combination of chips that embody VLSI's intellectual property connected by what would become the on-chip buses. Also included is memory, slots for peripheral cards, field-programmable memory and pins to connect to an in-circuit emulator. A designer would be able to model an ASIC by working with blocks of IP located on the prototyping chip or FPGA, or plugged into one of the board's data-bus slots. The first RSP board includes an ARM processor, the AMBA and VLSI on-chip buses, FPGAs and peripherals, such as infrared ports and UARTs. Currently, the boards include Gatefield FPGAs and sell for $19,000. Sales will begin later this month. Payne argues that the EDA industry is not moving quickly enough toward the less abstract, and therefore faster, methods of simulating complex designs with several million gates. Even RTL and cycle-accurate simulation models do little to ease the crunch. Rather than software simulation, the industry needs a combination of FPGAs and silicon reference designs where blocks are pre-wired into existing ASICs that can be placed on a development board optimized for a particular class of design, he said. Engineers working on a particular set-top-box design, for example, could use the prototyping chip provided by VLSI for that application. The designer could remove unneeded functions and add other, desired features. This "deconfiguring" and "configuring-in" process, combined with the on-chip bus architecture of the prototype ICs, "enables this feature-swapping design process to occur with assurance that the final design will perform as specified when first silicon is delivered," a spokesman said. Payne, who was the chief technology officer at VLSI for five years, said the growing distance between the number of gates possible in silicon and progress in simulation and verification will require new tools such as Velocity. "That is part of the reason why the semiconductor industry is in the situation we are in now," he said. "We are victims of our own silicon efficiency." Analyst Glover said VLSI, which has been rumored as a takeover candidate by larger ASIC vendors such as IBM Microelectronics or Lucent Technologies, needs Velocity to keep its own fabs filled and return to growth. "Semiconductor vendors have been in the trenches dealing with big-chip challenges for years, so it makes sense that they may actually precede the EDA industry in delivering unique and innovative solutions for designing complex systems-on-chip," she said. "And right now we really need all the good ideas we can get." Copyright ® 1998 CMP Media Inc.
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