VLSI design articles

Gerard M Blair

These are (mostly) in postscript; their full references can be found in the Publication Lists

1. Designing Low Power Digital CMOS

2. A review of the discrete Fourier transform: part 1
3. A review of the discrete Fourier transform: part 2
4. VLSI module design for the discrete cosine transform

5. Verilog - accelerating digital design

6. Bit-serial Spread-Spectrum Correlator Design with novel clocking technique

7. VLSI Sorting Circuit

8. Fast VLSI Adder Design
9. Twos-complement addition == redundant-binary conversion

10. Skew-Free Clock Distribution for Standard-Cell VLSI Designs
11. CMOS Buffer Tapering with Interconnect Capacitances
12. Self-generating clock using an augmented distribution network
13. Local generation of falling clock edge

14. Low-power double-edge triggered flip-flop
15. Comment on new flipflops from Afghahi
16. Comment on new differential flipflops from Yuan and Svensson

17. Reduced complexity, two-phase micro-pipeline data controller
18. Serial-parallel converter using micro-pipelines

Link to Verilog for Synchronous Digital Design teaching/resource area.

Gerard M Blair was a Senior Lecturer in VLSI Design and Project Management in the Department of Electrical Engineering, The University of Edinburgh, Scotland UK. He welcomes feedback either by email gerard@ee.ed.ac.uk or by other methods found here