module ttype(q, clk, reset, t);

   output q;
   input  clk, reset, t;
   reg	  q;

   always@(posedge clk)
      if (reset) q = 1'b0;
      else
	 if (t) q = ~q;

endmodule // t_type

module stimulus;
   
   reg clk, reset, t;
   wire	out;
   integer i;

   ttype t_test(out, clk, reset, t);

   initial begin
      clk = 1'b0;
      forever #5 clk = ~clk;
   end

   initial begin
      $display($time, "  t - out");
      for (i = 0; i < 32; i = i + 1) begin
	 t = i[2];
	 #10 $display ($time, "  %b -  %b", t, out);
      end
      #10 $finish;
   end

   initial begin
      reset = 1'b0;
      #60  reset = 1'b1;
      #40  reset = 1'b0;
      #100 reset = 1'b1;
      #30  reset = 1'b0;
   end

endmodule // stimulus