module dtype(q, clk, d);
   
   output q;
   input  clk, d;
   reg	  q;
   
   always @(posedge clk)
      q = d;
   
endmodule

module inv_mux(out, cnt, a, b);

   output out;
   input  cnt, a, b;

   assign out = (cnt) ? ~b : ~a;

endmodule // inv_mux

module dtype_er(q, clk, reset, enable, d);

   output q;
   input  clk, reset, enable, d;
   wire	  mux_out, nor_out;

   inv_mux i_m   (mux_out, enable, q, d);
   nor           (nor_out, reset, mux_out);
   dtype dtest_er(q, clk, nor_out);
   
endmodule // dtype_er


module stimulus;
   
   reg	   clk, reset, enable, d;
   wire	   q;
   integer i;
   
   dtype_er der_test(q, clk, reset, enable, d);
   
   initial begin
      clk = 1'b0;
      forever #5 clk = ~clk;
   end
   
   initial
      $display($time, " i = %b, reset = %b, enable = %b, d = %b, q = %b", 
	       i[3:0], reset, enable, d, q);
   
   always@(posedge clk) 
      #1 $display($time, " i = %b, reset = %b, enable = %b, d = %b, q = %b", 
		  i[3:0], reset, enable, d, q);
   
   initial begin
      d = 1'b0;
      reset = 1'b0;
      enable = 1'b0;
      for (i = 0; i < 16; i = i + 1) begin
	 #10 d  = i[0];
	 reset  = i[2];
	 enable = i[3];
      end      
      #10 $finish;
   end
   
endmodule // stimulus