module dtype_er(out, clk, reset, enable, d);
   
   output out;
   input  clk, reset, enable, d;
   reg	  out;
   
   always @(posedge clk)
      if (reset)
	 out = 0;
      else if (enable)
	 out = d;
   
endmodule

module stimulus;
   
   reg	   clk, reset, enable, d;
   wire	   q;
   integer i;
   
   dtype_er der_test(q, clk, reset, enable, d);
   
   initial begin
      clk = 1'b0;
      forever #5 clk = ~clk;
   end
   
   initial
      $display($time, " i = %b, reset = %b, enable = %b, d = %b, q = %b", 
	       i[3:0], reset, enable, d, q);
   
   always@(posedge clk) 
      #1 $display($time, " i = %b, reset = %b, enable = %b, d = %b, q = %b", 
		  i[3:0], reset, enable, d, q);
   
   initial begin
      d = 1'b0;
      reset = 1'b0;
      enable = 1'b0;
      for (i = 0; i < 16; i = i + 1) begin
	 #10 d  = i[0];
	 reset  = i[2];
	 enable = i[3];
      end      
      $finish;
   end
   
endmodule // stimulus