module dtype_r(out, clk, reset, d); output out; input clk, reset, d; reg out; always @(posedge clk) if (~reset) out = 0; else out = d; endmodule module stimulus; reg clk, reset, d; wire q; integer i; dtype_r dr_test(q, clk, reset, d); initial begin clk = 1'b0; forever #5 clk = ~clk; end initial $display($time, " i = %b, reset = %b, d = %b, q = %b", i[2:0], reset, d, q); always@(posedge clk) #1 $display($time, " i = %b, reset = %b, d = %b, q = %b", i[2:0], reset, d, q); initial begin d = 1'b0; reset = 1'b0; for (i = 0; i < 16; i = i + 1) begin #10 d = i[0]; reset = i[2]; end $finish; end endmodule // stimulus