module dtype(q, clk, d);
   
   output q;
   input  clk, d;
   reg	  q;
   
   always @(posedge clk)
      q = d;
   
endmodule

module dtype_4(q, clk, d);
   
   output [3:0]	q;
   input	clk;
   input [3:0]	d;
   
   dtype d0(q[0], clk, d[0]);
   dtype d1(q[1], clk, d[1]);
   dtype d2(q[2], clk, d[2]);
   dtype d3(q[3], clk, d[3]);
   
endmodule

module stimulus;

   reg	      clk;
   reg [3:0]  d;
   wire [3:0] q;
   integer    i;
   
   dtype_4 d_test_4(q, clk, d);

   initial begin
      clk = 1'b0;
      forever #5 clk = ~clk;
   end

   initial
      $display($time, " i = %b, d = %b, q = %b", i[2:0], d, q);
   
   always@(posedge clk) 
      #1 $display($time, " i = %b, d = %b, q = %b", i[2:0], d, q);

   initial begin
      d = 4'b0;
      for (i = 0; i < 16; i = i + 1)
	 #10 d = {i[2], {2{i[0]}}, i[1]};
      $finish;
   end

endmodule // stimulus