module dtype(q, clk, d);
   
   output q;
   input  clk, d;
   reg	  q;
   
   always @(posedge clk)
      q = d;
   
endmodule

module stimulus;

   reg	clk, d;
   wire	q;
   integer i;

   dtype d_test(q, clk, d);

   initial begin
      clk = 1'b0;
      forever #5 clk = ~clk;
   end

   initial
      $display($time, " i = %b, d = %b, q = %b", i[2:0], d, q);
   
   always@(posedge clk) 
      #1 $display($time, " i = %b, d = %b, q = %b", i[2:0], d, q);

   initial begin
      d = 1'b0;
      for (i = 0; i < 16; i = i + 1)
	 #10 d = (i[0] | i[2]);
      $finish;
   end

endmodule // stimulus