// positive edge-triggered four-bit dtype  

module dff(q, data, clock);
   output [3:0]	q;
   input [3:0]	data;
   input	clock;
   reg [3:0]	q;
   
   always @(posedge clock)
      q = data;
endmodule // dff

// gate-level description of shift register that delays the input signal 
// 3 clock cycles

module shift1( q, data, clock);
   output [3:0]	q;
   input [3:0]	data;
   input	clock;
   wire [3:0]	q1,q2,q3;
 
   dff mod1( q1, data, clock);
   dff mod2( q2, q1, clock);
   dff mod3( q3, q2, clock);
   dff mod4( q, q3, clock);

endmodule // shift


// behavioural-level description of shift register that delays the input 
// signal 3 clock cycles

module shift2( q, data, clock);
   output [3:0]	q;
   input [3:0]	data;
   input	clock;
   reg [3:0]	regMem[3:0];
   
   assign q = regMem[3];

   always @(posedge clock) begin
      regMem[3] = regMem[2];
      regMem[2] = regMem[1];
      regMem[1] = regMem[0];
      regMem[0] = data;
   end // always @ (posedge clock)
   
endmodule // shift2

module stimulus;
   reg [3:0]  data;
   reg clock;
   wire	[3:0] q1,q2;

   initial begin
      clock = 1'b0;
      forever #2 clock = ~clock;
   end
   
   shift1 shiftmod1( q1, data, clock);
   shift2 shiftmod2( q2, data, clock);
   
   initial begin
      data = 0;
      forever #4 data = data+1;
   end

   initial
      #1 forever #2 $display($time, " clk = %b data = %d q1 = %d q2 = %d ", 
			     clock, data, q1, q2);
   
   initial #40 $finish;

endmodule