// positive edge-triggered one-bit dtype  

module dff(q, data, clock);
   output q;
   input  data, clock;
   reg	  q;
   
   always @(posedge clock)
      q = data;
endmodule // dff

// gate-level description of shift register that delays the input signal 
// 3 clock cycles

module shift1( q, data, clock);
   output q;
   input  data, clock;
   wire	  q1,q2,q3;
 
   dff mod1( q1, data, clock);
   dff mod2( q2, q1, clock);
   dff mod3( q3, q2, clock);
   dff mod4( q, q3, clock);

endmodule // shift


// behavioural-level description of shift register that delays the input 
// signal 3 clock cycles

module shift2( q, data, clock);
   output    q;
   input     data, clock;
   reg [2:0] regMem;
   reg	     q;

   always @(posedge clock)
      {q, regMem} = {regMem, data};

endmodule // shift2

module stimulus;
   reg	data, clock;
   wire	q1,q2;

   initial begin
      clock = 1'b0;
      forever #2 clock = ~clock;
   end
   
   shift1 shiftmod1( q1, data, clock);
   shift2 shiftmod2( q2, data, clock);
   
   initial begin
      data = 1'b0;
      forever #4 data = ~data;
   end

   initial
      #1 forever #2 $display($time, " clk = %b data = %b q1 = %b q2 = %b ", 
			     clock, data, q1, q2);
   
   initial #40 $finish;

endmodule