Verilog Switch Level Modelling

Ambiguous Signal Strengths



Within switch level modelling, net connections can take scaler values, indicating the strength of the driven logic signal, either '1' or '0'.

One way of representing this value is through the use of two bytes of information; the first indicating the strength of the '0' portion of the net value, the second relating to the strength of the '1' portion of the net value.


            7  6  5  4  3  2  1  0    ||    7  6  5  4  3  2  1  0

                  '0' Strength                 '1' Strength

The bit positions within each byte correspond to the strength level values, the most significant (7) corresponding to the highest strength (supply drive) and the least significant (0) to a high impedance signal strength (z).

The logic value of a net is determined from the strength bytes. The example of verilog code below describes the coversion from the 16 bit strength value (inVal) to a three valued logic (log3) which can be either 0, 1 or x.

           //Convert full strength value to 3 valued logic

           function [1:0] log3;

           input [15:0] inVal;

           begin
              casez (inVal)
                  16'b00000000_00000000: log3 = ValX;
                  16'b???????0_00000000: log3 = Val0;
                  16'b00000000_???????0: log3 = Val1;
                  default: log = ValX;
           end;

           endfunction;

If all bits of each byte are zero, the value is unknown (x). If only some of the '0' strength bits are non-zero, the value will be a '0' and if only some of the '1' strength bits are non-zero, the value will be a '1'.
Otherwise, if bits of both sides of the strength bytes are set, the value will be an 'x'.

Ambiguous strengths arise when mutliple gates drive a common net or where an unknown value drives a control input. In these situations, the verilog model allows the net to take on a range of values, shown by consecutive bits in the strength bytes being set.
For example, in the following case a strong '1' and a strong '0' are two driven outputs competing for the same net. The outcome is an amibguous 'x' shown by bits on both sides of the strength bytes being non-zero and consecutive bits being set. This signifies the result could either be a '0' or '1' of varying strength.

		Output 1             00000000:01000000   =   1
		Output 2             01000000:00000000   =   0
		----------------------------------------------
		Result               01111111:01111111   =   x

Another example is where a pull '1' and an unknown with ambiguous strength both drive the net. The result is a '1' with ambiguous strengths of strong and pull as the highest zero strength of the x would always be defeated by the pull '1'.

		Output 1             00000000:00100000   =   1
		Output 2             00000111:01111111   =   x
		----------------------------------------------
		Result               00000000:01100000   =   1