Event-Based

Syntax:
event_control_statement::==
@ event_identifier
| @ (event_expression)

event_expression::==
| exp
| event_id
| posedge exp
| negedge exp
| event_exp or event_exp.

Event-based timing control allows conditional execution based on the occupance of a named event. Verilog waits on a predefined signal or a user defined variable to change before it executes a block.

        @ (clock) a = b;          // when the clock changes value, execute a = b

        @ (negedge clock) a = b;  // when the clock change to a 0, execute a=b

        a = @(posedge clock) b;   // evaluate b immediately and assign to a on
                                  // a positive clock edge.

Triggers

Triggers can be understood from the following example.

        event data_in;                 // user-defined event

        always @(negedge clock)
           if (data[8]==1) -> data_in; // trigger the event

        always @(data_in)              // event triggered block
           mem[0:1] = buf;