Design Blocks

Modules

The E-type flip flop is made of a D-type flip flop, an inverting multiplexor and a nor gate. We see this hierarchy in the figure below. We can break the mutliplexor down further but this level of detail is sufficient for this section.

There are two angles to approach the design of the E-type flip flop in Verilog:
Topdown- start with the E-type flip flop and add more detail.
Bottom up- start with the basic flip flop an inverting multiplexor and a nor gate, and build up, ie generalise the detail.

We will use a bottom up methodology, but typically a combination of both is used.

We start with the D-type, it is encapsulated as a module, enclosed in the keywords
module <module_name> ... endmodule, as below.

        module dff(q, data, clock);
           output q;
           input  data, clock;
           reg      q;

           always @(posedge clock)
              q = data;
        endmodule // dff

Now we need an inverting multiplexor and we similarly describe it by its behaviour.

        module mux2_1(out, in1, in2, cntrl);
           output out;
           input  in1, in2, cntrl;

           assign out = cntrl ? ~in1 : ~in2;
        endmodule // mux2_1

The top level E-type will use the functionality enclosed in the D-type and the multiplexer. To call a module we have to call it by name and give it another name by which it will be known in the higher level module.

        module e_ff(q, data, enable, reset, clock);
           output q;
           input  data, enable, reset, clock;
           wire     norout, muxout;

           mux2_1 mod1 (muxout, data, q, enable);
           nor         (norout, reset, muxout);
           dff    dff0 (q, norout, clock);
        endmodule

To instantiate, ie. call and use, a users defined modue we use the syntax
name_of_module instance_name (port_list);

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