In this section we will work through a Verilog design line by line. This section is for those who want to jump ahead and get a full flavour of the language before learning all the nitty gritty.
The example program will be a 4 to 1 multiplexor and will be implemented using three method, each a higher level of abstraction than the last.
Below is a logic diagram for a 4 to 1 multiplexor.