Verilog Input Vectors

To create input vectors for our simulations, we need only a very small subset of Verilog. These pages give some examples 

        initial
        begin
           clk = 1'b0;
           globalReset = 1'b1;
           in = 1'b1;
        end

The expression: 1'b0 indicates a binary number of value 0. In fact, for setting the values zero and one, you need only type 0 and 1.

There are two main sections: 

        initial
        begin
             -----
        end

        always
        begin
             -----
        end

Notice that "blocks" of code in Verilog are "bracketed" by the keywords begin and end - in C this is done by "{" and "}".

The initial block is started at the beginning of the simulation. Thus it is the place to initialize signals and to define a sequence of signal changes.

The always clock is a sequence of signals which is repeated throughout the simulation.

The delay between signal changes (or events) is specified by a number following a # sign. Thus: 

           #160 globalReset = 0;
           #160 in = 0;
           #160 in = 1;
           #320 in = 0;

says: wait 160 time units and set globalReset to zero, then wait 160 time units and set the in to zero, then etc

Notice that the delay is measured from the last event rather than from the beginning of the simulation.

The most common us of the always block is to define the clock signal. The following: 

        always
        begin
           #10 clk = ~clk;
        end

says that clk should be set to the inverse of the value of clk every 10 time units - which defines a clock signal of period 20 time units.

Thus the general approach is to setup the clock and other regularly alternating signals in always blocks and to define the sequence of changing signals in the initial block.

Warning: it is wise to end the initial block with a statement: 

        #<delay> $finish;

This causes the simulation to finish at the end of the initial block - if this is not present, the interactive simulation will continue until you press the interrupt button on the interactive simulator panel (probably long after useful information has been produced).

The repeat command may be useful. If you have a sequence of signal changes with is repeated for a given number (say 10) times then this can be coded as follows: 

        repeat(10)
        begin
            #40 in = 0;
            #20 in = 1;
        end

These repeat blocks may be nested.

One further command may be useful: a random number generator. The following produces numbers in the range [0, n-1]: 

        {$random} % n

(The smudgy character is the percent sign "%" - which is difficult to read in some netscape fonts).

The exception is random ones and zeros because some random number generators are not quite random in the least significant bit (lsb). For this it is necessary to divide the first term by an even number to remove the lsb before the modulus operation. 

        {$random} / 16  % 2

Combining these two commands we have the following which is a sequence of 14 random inputs changing ever 20 time units: 
        repeat(14)
        begin
            #20 in = {$random} / 16  % 2;
        end

Note: