The GATEWAY laboratory

An introduction to digital design using Verilog

The laboratory consists of seven formal sessions run over two terms. However, you may use the software at any time and are encouraged to do so - in fact, we expect that you will need twice the time allocated to the formal sessions to complete the learning.

The formal sessions are run in small groups (of about 20-25) so that you can have access to help - outwith these times, questions will normally be deferred until a formal session.

Autumn Term

Session 1: learning the environment and basics of Verilog language. All the necessary material is on-line (through the EE3 Web area).

Session 2: more on Verilog: especially delays.

Session 3: the beginings of system design

Spring Term

This term is a major design exercise. You will be given a paper which describes a function which you will then implement in Verilog by creating at least a behavioural and a gate-level model (to allow you to verify the latter by the former).

Deliverables

There are three deliverables:

1. A report on the design performed in Session 3 (25%)
2. A report on the Spring term design (50%)
3. The Verilog code associated with the Spring term design (25%)

It is perhaps worth noting that the Gateway exercise is worth 10% of the single-honours' mark.

Report Structure

The two reports will both be in the style (and of the size of) an IEE Electronics Letter - which can be found in the library. There are also examples on-line on the Gateway home page.

As a guideline, you have to distil the information to 750-1250 words plus 2-3 diagrams - but the details of length are best read in the journal itself. In practice, this means that the report is much shorter than requested for other laboratories BUT of a standard which could be published in a professional journal.