VHDL Simulation #1, DUE Tuesday June 8, classtime


Introduction

This simulation exposes the student some modeling topics not covered in the VHDL synthesis course; namely File IO, timing modeling, and VHDL configurations.

To Do

Setup

All entities required by this assignment are to be placed in a VHDL library called 'sim1'. Follow the procedures listed in this document to create the new library.

timecheck entity

Write the architecture for the VHDL entity shown below: 

entity timecheck is
  generic (
	  thd:     time := 0 ps;      -- hold time
	  tsu:     time := 0 ps;      -- setup time
	  tpwh:     time := 0 ps;     -- pulse width high min
	  tpwl:     time := 0 ps;     -- pulse width low minimum
	  spikefilt: time:= 0 ps;     -- spike rejection 
	  wd_d:      time := 0 ps;    -- wire delay, d input
	  wd_clk:      time := 0 ps   -- wire delay, clk input
	);

  port (
	clk : in std_logic;           -- input port
	d : in std_logic              -- input port
	);

end timecheck;

The architecture for the 'timecheck' entity is to do the following:

  1. Generate internal signals for inputs 'clk', 'd' that are delayed by the time specifed in 'wd_clk' and 'wd_d'. The internal signals should perform spike rejection of duration as specifed by 'spikefilt'.
  2. For a 1 to 0 transition on the internal 'clk' signal, do setup and hold time checking on the 'd' internal signal as specifed by the 'thd' and 'tsu' values.
  3. For the internal clock signal, do pulse width high/low checking as specifie by the 'tpwh' and 'tpwl' values.

The timing violations should be written in the following format: 

'violation message' : 'timeval_found' < 'timeval_required'
Examples are: 
setup time violation: 0.01 ns < 0.05 ns
clock min pulse width high violation: 0.01 ns < 0.3 ns
clock min pulse width low violation: 0.01 ns < 0.5 ns
setup time violation: 0.045 ns < 0.05 ns
hold time violation: 0.07 ns < 0.075 ns

These messages should be generated via a 'report' statement inside of an 'assertion' statement of severity 'warning'. It is VERY IMPORTANT that this wording be used. The 'qvsim' wraps some additional text around the output of the report statement so the complete output will look like: 

#    Time: 1050 ps  Iteration: 0  Instance:/tc
# ** Warning: 
setup time violation: 0.045 ns < 0.05 ns
Signal initialization (events at time 0) usually cause false timing violations to be reported; this is ok.

stimfile entity

Write the architecture for the VHDL entity shown below: 
entity stimfile is
	generic (
	  fname : string := "in.dat" 
	);

	port (
	  o : out std_logic
	);

end stimfile;

The architecture is read lines from a file which each line looks like: 

std_logic_value  time
Examples are: 
0  0 ps
1  100 ps
Z  200 ps
X  400 ps
The timevalue is the time at which that value should be applied to the 'o' output port. The architecture should continue to read lines out of the file named via the 'fname' generic until there are no more lines in the file.

Testbench

Write a testbench that instantitiates two 'stimfile' components whose outputs are connected to the inputs of a 'timecheck' component. Write input files for the stimfile components that check all of the timing violations reported by the 'timecheck' component.

To Turn In

All of your VHDL files should be in a directory called 'sim1' if you followed the directions for creating a new library. From the directory above 'sim1', copy the script submit_sim1.pl . Then execute the script via "perl submit_sim1.pl" This will create a compressed tar file of your 'sim1' directory and will mail it to me.

Other Constraints

I have listed some other constraints that you need to follow in order to make your architecture compatible with my testbench:

  1. Do not use seperate files for entity/architecture. Put the entity and architecture in the same file; name the file 'entityname.vhd'. (all lowercase). You should have files named "timecheck.vhd", "stimfile.vhd". Also include files for testbench ( "tb.vhd") , and ("cfg_tb.vhd") but I will not use them in my simulation, I will only check that you have them.
  2. Here are sample input files for the 'd'( d.dat ) and 'clk' ( clk ) inputs. Here is the output file that should result from these timings ( gold.sim1.log ). I WILL CHECK your file with OTHER TIMINGS - you need to test your model with other timings to verify functionality. . I will check your timecheck entities with different values for setup/hold/pulsewidth/wire delays.
  3. The generic values that produced the 'gold.sim1.log' file above were: thd = 75 ps, tsu = 50 ps, tpwh = 300 ps, tpwl = 500 ps, spikefile = 5 ps, wd_d = 10 ps, wd_clk = 20 ps. I will use different values for these generics and different input files for 'clk' and 'd' when I test your files.