4-to-1 mux with 8 bit Datapaths

library ieee;

use ieee.std_logic_1164.all;

entity mux4to1_8 is

   port ( a,b,c,d : in std_logic_vector(7 downto 0);

             sel: in std_logic_vector (1 downto 0);

            dout: out std_logic_vector(7 downto 0)

  );

end mux4to1_8;

architecture whenelse of mux4to1_8  is

begin

dout <=  b when (sel = "01") else

                c  when (sel  = "10") else

               d when (sel = "11") else

                a;      -- default

end process;

end whenelse;

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