PPT Slide

library ieee;

use ieee.std_logic_1164.all;

entity priority is

   port ( y1, y2, y3, y4, y5, y6, y7 : in std_logic;

            dout: out std_logic_vector(2 downto 0)

  );

end priority;

architecture ifels of priority  is

begin

-- priority circuit, Y7 highest priority input

-- Y1 is lowest priority input

process (y1, y2,y3, y4, y5, y6, y7)

begin

if (y7 = '1') then dout <= "111";

elsif (y6 = '1') then dout <= "110";

elsif (y5 = '1') then dout <= "101";

elsif (y4 = '1') then dout <= "100";

elsif (y3 = '1') then dout <= "011";

elsif (y2 = '1') then dout <= "010";

elsif (y1 = '1') then dout <= "001";

else dout <= "000";

end process;

end ifels;

This priority circuit has 7 inputs; Y7 is highest priority, Y0 is lowest priority. 

Three bit output should indicate the highest priority input that is a '1' (ie. if  Y6 ='1' , Y4 = '1', then output should be "101").  If no input is asserted, output should be "000".

Priority circuit example

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