How do I add DFFs to FSM outputs?
In two process VHDL model, explicity add DFFs via separate signals
comblogic: process (zero, cnt_eq, pstate) begin
stateff:process(clk) -- process has DFFs only
if (reset = '1') then pstate <= S0;
elsif (clk'event and clk='1') then
pstate <= nstate; -- updated present state with next state ld_cnt_dly <= ld_cnt; -- DFF on ld_cnt line. Connect
endif; -- ld_cnt_dly to counter end process stateff;