Field Programmable Gate Arrays
The FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them.
What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”.
- A primitive gate like a NAND gate
- A 2/1 mux (this happens to be a complete logic family)
- A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic function).
Often combine one of the above with a DFF to form the primitive logic element.