Gate Array
Designer uses a library of standard cells. The design is mapped onto an array of transistors which is already created on a wafer; wafers with transistor arrays can be created ahead of time. A routing tool creates the masks for the routing layers and "customizes" the pre-created gate array for the user's design.
Transistor density can be almost as good as standard cell. Design time advantages are the same as for standard cell.
Performance can be very good; again, depends on quality of available library and routing tools.