Minimum External Setup Time Data latched in IOE
Tsu_ext = Tinreg + Tiosu - minimum(Tdclk2le)
Tsu_ext = 6.0 ns + 2.8 - 0 = 8.8 ns
!! Latching in IOE slower than in Logic Element? These are all worse case numbers in the datasheet which could account for this; also mentioned on page 28 that latching in LE element will sometimes give better setup time than an IOE. For other FPGA families this is usually not the case.