SSN Combinational Decode Lab for EE 3714

This form will allow you to compile/simulate your VHDL file for the SSN decode lab in EE 3714.

Step #1

You must first prepare a VHDL file that implements the boolean logic for your SSN decoder. Right click on this link and save this file to your local disk. This is a VHDL file that can be used as starting point for your VHDL solution. A VHDL file that has the solution for SSN = "458 70 2198" is available here . You might want to try compiling/simulating this file using the procedure below to see what type of results you should expect.

Step #2

Fill in the information below (Student ID number, and file name), and hit the submit button. If successful, you will be returned an HTML page that has links to a JEDEC file (.jed) for a 22V10 PLD and a REPORT file (.rpt file). You should remember the URL (web address) of the RETURNED page so that you can program your 22V10 PLD during lab. You must enter your SSN in the field below and browse to a file on your local file system that contains your VHDL code.

If your VHDL file has syntax errors, the REPORT file will contain error messages from the parser that indicates the line numbers of the errors. I would suggest correcting only the FIRST error, and then trying again. Errors after the first error can be generated as a side effect of the first error, and may disappear after you correct the first error.

The simulation results will show the F1, F2, F3, F4 outputs for all combinations of the A,B,C,D inputs. Be sure that you check that these are the expected results. If they are NOT the expected results, then you need to check your boolean equations. There is no need to program the 22V10 PLD if your simulation results are not what you expect (because the 22V10 PLD will simply do what the simulation reports...).

You MUST have produced the JEDEC file and simulation file before you come to class. BEFORE you program the 22V10 PLD, you must show the TA that your simulation results match your expected results. DO NOT TIE UP THE PLD PROGRAMMER if your simulation results are incorrect.

Student ID number:

 

VHDL File:

 
 

 
 

Microsoft Internet Explorer Options

If you keep seeing the same report file or JEDEC file even when you change your VHDL file, then you might need to change your IE Explorer options. Under the 'View' menu choice at the top bar, select 'Internet Options'. In the "Internet Options" form, under "Temporary Internet Files", choose the "Settings" button. In the "Settings" form under "Check for newer versions of stored pages", make sure that "Every visit to the page" is selected. Once you have done this, this exit all of the forms by clicking on the "Ok" button at the bottom of each form.

Last modified: Mon Sep 20 16:09:32 CDT 1999